From: Chintan Vankar <c-vankar@ti.com>
To: Andrew Davis <afd@ti.com>,
Siddharth Vadapalli <s-vadapalli@ti.com>,
"Conor Dooley" <conor+dt@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
"Rob Herring" <robh@kernel.org>, Tero Kristo <kristo@kernel.org>,
"Vignesh Raghavendra" <vigneshr@ti.com>,
Nishanth Menon <nm@ti.com>
Cc: <linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>, <c-vankar@ti.com>
Subject: [PATCH] arm64: dts: ti: k3-j721e: Fix QSGMII overlay by adding SERDES PHY
Date: Thu, 26 Mar 2026 12:52:37 +0530 [thread overview]
Message-ID: <20260326072237.1324027-1-c-vankar@ti.com> (raw)
For CPSW9G QSGMII ports, CPSW assumes SERDES to be configured. Since it
may not be always true, add SERDES phys to guarantee it.
Fixes: 86e7de8bf908 ("arm64: dts: ti: k3-j721e: Add overlay to enable CPSW9G ports in QSGMII mode")
Signed-off-by: Chintan Vankar <c-vankar@ti.com>
---
This patch is based on commit "0138af2472df" of origin/master branch
of Linux repo.
arch/arm64/boot/dts/ti/k3-j721e-evm-quad-port-eth-exp.dtso | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-evm-quad-port-eth-exp.dtso b/arch/arm64/boot/dts/ti/k3-j721e-evm-quad-port-eth-exp.dtso
index 8376fa4b6ee1..d403a3db0265 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-evm-quad-port-eth-exp.dtso
+++ b/arch/arm64/boot/dts/ti/k3-j721e-evm-quad-port-eth-exp.dtso
@@ -42,7 +42,8 @@ &cpsw0_port2 {
phy-handle = <&cpsw9g_phy1>;
phy-mode = "qsgmii";
mac-address = [00 00 00 00 00 00];
- phys = <&cpsw0_phy_gmii_sel 2>;
+ phys = <&cpsw0_phy_gmii_sel 2>, <&serdes0_qsgmii_link>;
+ phy-names = "mac", "serdes";
};
&cpsw0_port3 {
--
2.34.1
next reply other threads:[~2026-03-26 7:22 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-26 7:22 Chintan Vankar [this message]
2026-03-27 5:15 ` [PATCH] arm64: dts: ti: k3-j721e: Fix QSGMII overlay by adding SERDES PHY Vignesh Raghavendra
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