From: Chintan Vankar <c-vankar@ti.com>
To: Siddharth Vadapalli <s-vadapalli@ti.com>,
Andrew Davis <afd@ti.com>, "Conor Dooley" <conor+dt@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
"Rob Herring" <robh@kernel.org>, Tero Kristo <kristo@kernel.org>,
"Vignesh Raghavendra" <vigneshr@ti.com>,
Nishanth Menon <nm@ti.com>
Cc: <linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>, <c-vankar@ti.com>
Subject: [PATCH] arm64: dts: ti: k3-j7200: Fix QSGMII overlay by adding SERDES PHY
Date: Thu, 26 Mar 2026 19:19:29 +0530 [thread overview]
Message-ID: <20260326134929.1696750-1-c-vankar@ti.com> (raw)
For CPSW5G QSGMII ports, CPSW assumes SERDES to be configured. Since it
may not be always true, add SERDES phys to guarantee it.
Fixes: 496cdc82e05f ("arm64: dts: ti: k3-j7200: Add overlay to enable CPSW5G ports in QSGMII mode")
Signed-off-by: Chintan Vankar <c-vankar@ti.com>
---
This patch is based on commit "0138af2472df" of origin/master branch of
Linux repo.
arch/arm64/boot/dts/ti/k3-j7200-evm-quad-port-eth-exp.dtso | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-evm-quad-port-eth-exp.dtso b/arch/arm64/boot/dts/ti/k3-j7200-evm-quad-port-eth-exp.dtso
index 6432ca08ee8e..4824d53c95bb 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-evm-quad-port-eth-exp.dtso
+++ b/arch/arm64/boot/dts/ti/k3-j7200-evm-quad-port-eth-exp.dtso
@@ -32,7 +32,8 @@ &cpsw0_port1 {
phy-handle = <&cpsw5g_phy0>;
phy-mode = "qsgmii";
mac-address = [00 00 00 00 00 00];
- phys = <&cpsw0_phy_gmii_sel 1>;
+ phys = <&cpsw0_phy_gmii_sel 1>, <&serdes0_qsgmii_link>;
+ phy-names = "mac", "serdes";
};
&cpsw0_port2 {
--
2.34.1
reply other threads:[~2026-03-26 13:49 UTC|newest]
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