Re: [PATCH v3 1/2] dt-bindings: perf: marvell: Document CN20K DDR PMU

[Krzysztof Kozlowski <krzk@kernel.org>]

On Wed, Apr 01, 2026 at 01:46:39PM +0530, Geetha sowjanya wrote:
> Add a devicetree binding for the Marvell CN20K DDR performance
> monitor block, including the marvell,cn20k-ddr-pmu compatible
> string and the required MMIO reg region.

You just repeated the diff. No need, we can read the diff, but what we
cannot read is the hardware you are here describing.

> 
> Signed-off-by: Geetha sowjanya <gakula@marvell.com>
> ---
>  .../bindings/perf/marvell-cn20k-ddr.yaml      | 39 +++++++++++++++++++

So you did not test v1. You did not test v2.

Did you finally test this one before sending?

>  1 file changed, 39 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/perf/marvell-cn20k-ddr.yaml
> 
> diff --git a/Documentation/devicetree/bindings/perf/marvell-cn20k-ddr.yaml b/Documentation/devicetree/bindings/perf/marvell-cn20k-ddr.yaml
> new file mode 100644
> index 000000000000..fa757017d66e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/perf/marvell-cn20k-ddr.yaml
> @@ -0,0 +1,39 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/perf/marvell-cn20k-ddr.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Marvell CN20K DDR performance monitor
> +
> +description:
> +  Performance Monitoring Unit (PMU) for the DDR controller
> +  in Marvell CN20K SoCs.
> +
> +maintainers:
> +  - Geetha sowjanya <gakula@marvell.com>
> +
> +properties:
> +  compatible:
> +    const: marvell,cn20k-ddr-pmu

There is no such thing as marvell,cn20k in upstream. What's that?

Best regards,
Krzysztof