From: Steffen Eiden <seiden@linux.ibm.com>
To: kvm@vger.kernel.org, kvmarm@lists.linux.dev,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-s390@vger.kernel.org
Cc: Andreas Grapentin <Andreas.Grapentin@ibm.com>,
Arnd Bergmann <arnd@arndb.de>,
Catalin Marinas <catalin.marinas@arm.com>,
Christian Borntraeger <borntraeger@linux.ibm.com>,
Claudio Imbrenda <imbrenda@linux.ibm.com>,
David Hildenbrand <david@kernel.org>,
Gautam Gala <ggala@linux.ibm.com>,
Hendrik Brueckner <brueckner@linux.ibm.com>,
Janosch Frank <frankja@linux.ibm.com>,
Joey Gouly <joey.gouly@arm.com>, Marc Zyngier <maz@kernel.org>,
Nina Schoetterl-Glausch <oss@nina.schoetterlglausch.eu>,
Oliver Upton <oupton@kernel.org>,
Paolo Bonzini <pbonzini@redhat.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Ulrich Weigand <Ulrich.Weigand@de.ibm.com>,
Will Deacon <will@kernel.org>, Zenghui Yu <yuzenghui@huawei.com>
Subject: [PATCH v1 08/27] arm64: Extract pstate definitions from ptrace
Date: Thu, 2 Apr 2026 06:21:04 +0200 [thread overview]
Message-ID: <20260402042125.3948963-9-seiden@linux.ibm.com> (raw)
In-Reply-To: <20260402042125.3948963-1-seiden@linux.ibm.com>
From: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
Split all definitions that can be used by non-native architectures into a
separate file pstate.h. This allows other architectures using
the pstate definitions. While at it refactor SPSR related definitions
to use the BIT(n) macro and move them into sysreg-defs.h
Signed-off-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
Signed-off-by: Steffen Eiden <seiden@linux.ibm.com>
---
arch/arm64/include/asm/ptrace.h | 34 +-----------------
arch/arm64/include/uapi/asm/Kbuild | 1 +
arch/arm64/include/uapi/asm/ptrace.h | 49 +------------------------
include/arch/arm64/asm/pstate.h | 46 ++++++++++++++++++++++++
include/arch/arm64/asm/sysreg-defs.h | 42 ++++++++++++++++++++++
include/uapi/arch/arm64/asm/pstate.h | 53 ++++++++++++++++++++++++++++
6 files changed, 144 insertions(+), 81 deletions(-)
create mode 100644 include/arch/arm64/asm/pstate.h
create mode 100644 include/uapi/arch/arm64/asm/pstate.h
diff --git a/arch/arm64/include/asm/ptrace.h b/arch/arm64/include/asm/ptrace.h
index 39582511ad72..72ea0a8af960 100644
--- a/arch/arm64/include/asm/ptrace.h
+++ b/arch/arm64/include/asm/ptrace.h
@@ -9,6 +9,7 @@
#define __ASM_PTRACE_H
#include <asm/cpufeature.h>
+#include <asm/pstate.h>
#include <uapi/asm/ptrace.h>
@@ -28,10 +29,6 @@
#define GIC_PRIO_PSR_I_SET GICV3_PRIO_PSR_I_SET
-/* Additional SPSR bits not exposed in the UABI */
-#define PSR_MODE_THREAD_BIT (1 << 0)
-#define PSR_IL_BIT (1 << 20)
-
/* AArch32-specific ptrace requests */
#define COMPAT_PTRACE_GETREGS 12
#define COMPAT_PTRACE_SETREGS 13
@@ -42,41 +39,12 @@
#define COMPAT_PTRACE_GETHBPREGS 29
#define COMPAT_PTRACE_SETHBPREGS 30
-/* SPSR_ELx bits for exceptions taken from AArch32 */
-#define PSR_AA32_MODE_MASK 0x0000001f
-#define PSR_AA32_MODE_USR 0x00000010
-#define PSR_AA32_MODE_FIQ 0x00000011
-#define PSR_AA32_MODE_IRQ 0x00000012
-#define PSR_AA32_MODE_SVC 0x00000013
-#define PSR_AA32_MODE_ABT 0x00000017
-#define PSR_AA32_MODE_HYP 0x0000001a
-#define PSR_AA32_MODE_UND 0x0000001b
-#define PSR_AA32_MODE_SYS 0x0000001f
-#define PSR_AA32_T_BIT 0x00000020
-#define PSR_AA32_F_BIT 0x00000040
-#define PSR_AA32_I_BIT 0x00000080
-#define PSR_AA32_A_BIT 0x00000100
-#define PSR_AA32_E_BIT 0x00000200
-#define PSR_AA32_PAN_BIT 0x00400000
-#define PSR_AA32_SSBS_BIT 0x00800000
-#define PSR_AA32_DIT_BIT 0x01000000
-#define PSR_AA32_Q_BIT 0x08000000
-#define PSR_AA32_V_BIT 0x10000000
-#define PSR_AA32_C_BIT 0x20000000
-#define PSR_AA32_Z_BIT 0x40000000
-#define PSR_AA32_N_BIT 0x80000000
-#define PSR_AA32_IT_MASK 0x0600fc00 /* If-Then execution state mask */
-#define PSR_AA32_GE_MASK 0x000f0000
-
#ifdef CONFIG_CPU_BIG_ENDIAN
#define PSR_AA32_ENDSTATE PSR_AA32_E_BIT
#else
#define PSR_AA32_ENDSTATE 0
#endif
-/* AArch32 CPSR bits, as seen in AArch32 */
-#define COMPAT_PSR_DIT_BIT 0x00200000
-
/*
* These are 'magic' values for PTRACE_PEEKUSR that return info about where a
* process is located in memory.
diff --git a/arch/arm64/include/uapi/asm/Kbuild b/arch/arm64/include/uapi/asm/Kbuild
index b45584e83448..43d1a8ab98e1 100644
--- a/arch/arm64/include/uapi/asm/Kbuild
+++ b/arch/arm64/include/uapi/asm/Kbuild
@@ -5,3 +5,4 @@ generic-y += kvm_para.h
shared-uapi-y += kvm.h
shared-uapi-y += sve_context.h
+shared-uapi-y += pstate.h
diff --git a/arch/arm64/include/uapi/asm/ptrace.h b/arch/arm64/include/uapi/asm/ptrace.h
index 6fed93fb2536..6e743eb021e8 100644
--- a/arch/arm64/include/uapi/asm/ptrace.h
+++ b/arch/arm64/include/uapi/asm/ptrace.h
@@ -24,54 +24,7 @@
#include <asm/hwcap.h>
#include <asm/sve_context.h>
-
-
-/*
- * PSR bits
- */
-#define PSR_MODE_EL0t 0x00000000
-#define PSR_MODE_EL1t 0x00000004
-#define PSR_MODE_EL1h 0x00000005
-#define PSR_MODE_EL2t 0x00000008
-#define PSR_MODE_EL2h 0x00000009
-#define PSR_MODE_EL3t 0x0000000c
-#define PSR_MODE_EL3h 0x0000000d
-#define PSR_MODE_MASK 0x0000000f
-
-/* AArch32 CPSR bits */
-#define PSR_MODE32_BIT 0x00000010
-
-/* AArch64 SPSR bits */
-#define PSR_F_BIT 0x00000040
-#define PSR_I_BIT 0x00000080
-#define PSR_A_BIT 0x00000100
-#define PSR_D_BIT 0x00000200
-#define PSR_BTYPE_MASK 0x00000c00
-#define PSR_SSBS_BIT 0x00001000
-#define PSR_PAN_BIT 0x00400000
-#define PSR_UAO_BIT 0x00800000
-#define PSR_DIT_BIT 0x01000000
-#define PSR_TCO_BIT 0x02000000
-#define PSR_V_BIT 0x10000000
-#define PSR_C_BIT 0x20000000
-#define PSR_Z_BIT 0x40000000
-#define PSR_N_BIT 0x80000000
-
-#define PSR_BTYPE_SHIFT 10
-
-/*
- * Groups of PSR bits
- */
-#define PSR_f 0xff000000 /* Flags */
-#define PSR_s 0x00ff0000 /* Status */
-#define PSR_x 0x0000ff00 /* Extension */
-#define PSR_c 0x000000ff /* Control */
-
-/* Convenience names for the values of PSTATE.BTYPE */
-#define PSR_BTYPE_NONE (0b00 << PSR_BTYPE_SHIFT)
-#define PSR_BTYPE_JC (0b01 << PSR_BTYPE_SHIFT)
-#define PSR_BTYPE_C (0b10 << PSR_BTYPE_SHIFT)
-#define PSR_BTYPE_J (0b11 << PSR_BTYPE_SHIFT)
+#include <asm/pstate.h>
/* syscall emulation path in ptrace */
#define PTRACE_SYSEMU 31
diff --git a/include/arch/arm64/asm/pstate.h b/include/arch/arm64/asm/pstate.h
new file mode 100644
index 000000000000..3ff6073a0eaa
--- /dev/null
+++ b/include/arch/arm64/asm/pstate.h
@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __ASM_PSTATE_H
+#define __ASM_PSTATE_H
+
+#include <asm/sysreg-defs.h>
+#ifdef __arm64__
+#include <uapi/asm/pstate.h>
+#else
+#include <uapi/arch/arm64/asm/pstate.h>
+#endif // __arm64__
+
+/* Additional SPSR bits not exposed in the UABI */
+#define PSR_MODE_THREAD_BIT BIT(0)
+#define PSR_IL_BIT SPSR_IL
+
+/* SPSR_ELx bits for exceptions taken from AArch32 */
+#define PSR_AA32_MODE_MASK SPSR_MODE_MASK
+#define PSR_AA32_MODE_USR (SPSR_MODE_32BIT | SPSR32_MODE_USR)
+#define PSR_AA32_MODE_FIQ (SPSR_MODE_32BIT | SPSR32_MODE_FIQ)
+#define PSR_AA32_MODE_IRQ (SPSR_MODE_32BIT | SPSR32_MODE_IRQ)
+#define PSR_AA32_MODE_SVC (SPSR_MODE_32BIT | SPSR32_MODE_SVC)
+#define PSR_AA32_MODE_ABT (SPSR_MODE_32BIT | SPSR32_MODE_ABT)
+#define PSR_AA32_MODE_HYP (SPSR_MODE_32BIT | SPSR32_MODE_HYP)
+#define PSR_AA32_MODE_UND (SPSR_MODE_32BIT | SPSR32_MODE_UND)
+#define PSR_AA32_MODE_SYS (SPSR_MODE_32BIT | SPSR32_MODE_SYS)
+#define PSR_AA32_T_BIT SPSR32_T
+#define PSR_AA32_F_BIT SPSR_F
+#define PSR_AA32_I_BIT SPSR_I
+#define PSR_AA32_A_BIT SPSR_A
+#define PSR_AA32_E_BIT SPSR32_E
+#define PSR_AA32_PAN_BIT SPSR_PAN
+#define PSR_AA32_SSBS_BIT SPSR32_SSBS
+#define PSR_AA32_DIT_BIT SPSR_DIT
+#define PSR_AA32_Q_BIT SPSR32_Q
+#define PSR_AA32_V_BIT SPSR_V
+#define PSR_AA32_C_BIT SPSR_C
+#define PSR_AA32_Z_BIT SPSR_Z
+#define PSR_AA32_N_BIT SPSR_N
+#define PSR_AA32_IT_MASK SPSR32_IT_MASK /* If-Then execution state mask */
+#define PSR_AA32_GE_MASK SPSR32_GE_MASK
+
+/* AArch32 CPSR bits, as seen in AArch32 */
+#define COMPAT_PSR_DIT_BIT 0x00200000
+
+#endif /* __ASM_PSTATE_H */
diff --git a/include/arch/arm64/asm/sysreg-defs.h b/include/arch/arm64/asm/sysreg-defs.h
index d5196f293e19..4460fae38623 100644
--- a/include/arch/arm64/asm/sysreg-defs.h
+++ b/include/arch/arm64/asm/sysreg-defs.h
@@ -470,6 +470,48 @@
#define SYS_FPEXC32_EL2 sys_reg(3, 4, 5, 3, 0)
#define SYS_TFSR_EL2 sys_reg(3, 4, 5, 6, 0)
+#define SPSR_PPEND BIT(33)
+#define SPSR_N BIT(31)
+#define SPSR_Z BIT(30)
+#define SPSR_C BIT(29)
+#define SPSR_V BIT(28)
+#define SPSR32_Q BIT(27)
+#define SPSR32_IT_MASK (GENMASK(26, 25) | GENMASK(15, 10))
+#define SPSR64_TCO BIT(25)
+#define SPSR_DIT BIT(24)
+#define SPSR64_UAO BIT(23)
+#define SPSR32_SSBS BIT(23)
+#define SPSR_PAN BIT(22)
+#define SPSR_SS BIT(21)
+#define SPSR_IL BIT(20)
+#define SPSR32_GE_MASK GENMASK(19, 16)
+#define SPSR64_SSBS BIT(12)
+#define SPSR64_BTYPE_SHIFT 10
+#define SPSR64_BTYPE_MASK (UL(3) << SPSR64_BTYPE_SHIFT)
+#define SPSR64_D BIT(9)
+#define SPSR32_E BIT(9)
+#define SPSR_A BIT(8)
+#define SPSR_I BIT(7)
+#define SPSR_F BIT(6)
+#define SPSR32_T BIT(5)
+#define SPSR_MODE_MASK UL(0x1f)
+#define SPSR_MODE_32BIT BIT(4)
+#define SPSR64_MODE_EL0 UL(0x0)
+#define SPSR64_MODE_EL1t UL(0x4)
+#define SPSR64_MODE_EL1h UL(0x5)
+#define SPSR64_MODE_EL2t UL(0x8)
+#define SPSR64_MODE_EL2h UL(0x9)
+#define SPSR64_MODE_EL3t UL(0xc)
+#define SPSR64_MODE_EL3h UL(0xd)
+#define SPSR32_MODE_USR UL(0x0)
+#define SPSR32_MODE_FIQ UL(0x1)
+#define SPSR32_MODE_IRQ UL(0x2)
+#define SPSR32_MODE_SVC UL(0x3)
+#define SPSR32_MODE_ABT UL(0x7)
+#define SPSR32_MODE_HYP UL(0xa)
+#define SPSR32_MODE_UND UL(0xb)
+#define SPSR32_MODE_SYS UL(0xf)
+
#define SYS_FAR_EL2 sys_reg(3, 4, 6, 0, 0)
#define SYS_HPFAR_EL2 sys_reg(3, 4, 6, 0, 4)
diff --git a/include/uapi/arch/arm64/asm/pstate.h b/include/uapi/arch/arm64/asm/pstate.h
new file mode 100644
index 000000000000..87b2acec9ac2
--- /dev/null
+++ b/include/uapi/arch/arm64/asm/pstate.h
@@ -0,0 +1,53 @@
+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
+
+#ifndef _UAPI__ASM_PSTATE_H
+#define _UAPI__ASM_PSTATE_H
+
+/*
+ * PSR bits
+ */
+#define PSR_MODE_EL0t 0x00000000
+#define PSR_MODE_EL1t 0x00000004
+#define PSR_MODE_EL1h 0x00000005
+#define PSR_MODE_EL2t 0x00000008
+#define PSR_MODE_EL2h 0x00000009
+#define PSR_MODE_EL3t 0x0000000c
+#define PSR_MODE_EL3h 0x0000000d
+#define PSR_MODE_MASK 0x0000000f
+
+/* AArch32 CPSR bits */
+#define PSR_MODE32_BIT 0x00000010
+
+/* AArch64 SPSR bits */
+#define PSR_F_BIT 0x00000040
+#define PSR_I_BIT 0x00000080
+#define PSR_A_BIT 0x00000100
+#define PSR_D_BIT 0x00000200
+#define PSR_BTYPE_MASK 0x00000c00
+#define PSR_SSBS_BIT 0x00001000
+#define PSR_PAN_BIT 0x00400000
+#define PSR_UAO_BIT 0x00800000
+#define PSR_DIT_BIT 0x01000000
+#define PSR_TCO_BIT 0x02000000
+#define PSR_V_BIT 0x10000000
+#define PSR_C_BIT 0x20000000
+#define PSR_Z_BIT 0x40000000
+#define PSR_N_BIT 0x80000000
+
+#define PSR_BTYPE_SHIFT 10
+
+/*
+ * Groups of PSR bits
+ */
+#define PSR_f 0xff000000 /* Flags */
+#define PSR_s 0x00ff0000 /* Status */
+#define PSR_x 0x0000ff00 /* Extension */
+#define PSR_c 0x000000ff /* Control */
+
+/* Convenience names for the values of PSTATE.BTYPE */
+#define PSR_BTYPE_NONE (0b00 << PSR_BTYPE_SHIFT)
+#define PSR_BTYPE_JC (0b01 << PSR_BTYPE_SHIFT)
+#define PSR_BTYPE_C (0b10 << PSR_BTYPE_SHIFT)
+#define PSR_BTYPE_J (0b11 << PSR_BTYPE_SHIFT)
+
+#endif /* _UAPI__ASM_PSTATE_H */
--
2.51.0
next prev parent reply other threads:[~2026-04-02 4:22 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-04-02 4:20 [PATCH v1 00/27] KVM: s390: Introduce arm64 KVM Steffen Eiden
2026-04-02 4:20 ` [PATCH v1 01/27] VFIO: take reference to the KVM module Steffen Eiden
2026-04-02 9:18 ` Paolo Bonzini
2026-04-02 4:20 ` [PATCH v1 02/27] KVM, vfio: remove symbol_get(kvm_get_kvm_safe) from vfio Steffen Eiden
2026-04-02 4:20 ` [PATCH v1 03/27] KVM, vfio: remove symbol_get(kvm_put_kvm) " Steffen Eiden
2026-04-02 4:21 ` [PATCH v1 04/27] arm64: Provide arm64 UAPI for other host architectures Steffen Eiden
2026-04-02 4:21 ` [PATCH v1 05/27] arm64: Extract sysreg definitions Steffen Eiden
2026-04-02 4:21 ` [PATCH v1 06/27] arm64: Provide arm64 API for non-native architectures Steffen Eiden
2026-04-02 4:21 ` [PATCH v1 07/27] KVM: arm64: Provide arm64 KVM " Steffen Eiden
2026-04-02 10:08 ` Marc Zyngier
2026-04-02 11:26 ` Christian Borntraeger
2026-04-02 4:21 ` Steffen Eiden [this message]
2026-04-02 4:21 ` [PATCH v1 09/27] KVM: arm64: Share kvm_emulate definitions Steffen Eiden
2026-04-02 4:21 ` [PATCH v1 10/27] KVM: arm64: Make some arm64 KVM code shareable Steffen Eiden
2026-04-02 4:21 ` [PATCH v1 11/27] KVM: arm64: Access elements of vcpu_gp_regs individually Steffen Eiden
2026-04-02 4:21 ` [PATCH v1 12/27] KVM: arm64: Share reset general register code Steffen Eiden
2026-04-02 4:21 ` [PATCH v1 13/27] KVM: arm64: Extract & share ipa size shift calculation Steffen Eiden
2026-04-02 4:21 ` [PATCH v1 14/27] KVM: s390: Move s390 kvm code into a subdirectory Steffen Eiden
2026-04-02 4:21 ` [PATCH v1 15/27] KVM: S390: Refactor gmap Steffen Eiden
2026-04-02 4:21 ` [PATCH v1 16/27] KVM: Make device name configurable Steffen Eiden
2026-04-02 4:21 ` [PATCH v1 17/27] KVM: Remove KVM_MMIO as config option Steffen Eiden
2026-04-02 4:21 ` [PATCH v1 18/27] KVM: s390: Prepare kvm-s390 for a second kvm module Steffen Eiden
2026-04-02 4:21 ` [PATCH v1 19/27] s390: Introduce Start Arm Execution instruction Steffen Eiden
2026-04-02 4:21 ` [PATCH v1 20/27] KVM: s390: arm64: Introduce host definitions Steffen Eiden
2026-04-02 4:21 ` [PATCH v1 21/27] s390/hwcaps: Report SAE support as hwcap Steffen Eiden
2026-04-02 4:21 ` [PATCH v1 22/27] KVM: s390: Add basic arm64 kvm module Steffen Eiden
2026-04-02 4:21 ` [PATCH v1 23/27] KVM: s390: arm64: Implement required functions Steffen Eiden
2026-04-02 4:21 ` [PATCH v1 24/27] KVM: s390: arm64: Implement vm/vcpu create destroy Steffen Eiden
2026-04-02 4:21 ` [PATCH v1 25/27] KVM: s390: arm64: Implement vCPU IOCTLs Steffen Eiden
2026-04-02 4:21 ` [PATCH v1 26/27] KVM: s390: arm64: Implement basic page fault handler Steffen Eiden
2026-04-02 4:21 ` [PATCH v1 27/27] KVM: s390: arm64: Enable KVM_ARM64 config and Kbuild Steffen Eiden
2026-04-02 8:53 ` [PATCH v1 00/27] KVM: s390: Introduce arm64 KVM David Hildenbrand (Arm)
2026-04-02 10:07 ` Christian Borntraeger
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