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Mon, 6 Apr 2026 16:20:43 -0700 From: Besar Wicaksono To: , , CC: , , , , , , , , , , , "Besar Wicaksono" Subject: [PATCH] perf/arm_pmu: Skip PMCCNTR_EL0 on NVIDIA Olympus Date: Mon, 6 Apr 2026 23:20:34 +0000 Message-ID: <20260406232034.2566133-1-bwicaksono@nvidia.com> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000AD82:EE_|PH8PR12MB6843:EE_ X-MS-Office365-Filtering-Correlation-Id: fc0d3098-7dbc-4b22-77db-08de94332a05 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|376014|36860700016|1800799024|18002099003|56012099003; X-Microsoft-Antispam-Message-Info: Yof1GB0YcJxeWlj4n1GpeawgPPEVxNJn1SPgm4al6Hxf9Vdf8rvIn9ak3C4Z3UWN9OVgELS1+l0JvFwD2ujzMCq5/u0auMZj9fdAy2X9uAdgKVJsuMHxA673lIwtwHQ7lfBw0ALI8sog0hPB3kv3Tbv2qXkf6/3wNCW/kebVjzXvVHrc+Y6zS19e0sPFAv1YzUQQOwHHFWEBm0J1Z7EEplxHilR6Rdba+Y3ZnLwAV3LRxqlxL2BulNoDQXHqOQ8+y15HwrHEyajkhumdM/tlpiOmbFPA4GRnqbBwGwDbhmXl79XIDPR/KAXWRGOGE2XmecR2SsbuNANN1cJHDxJLFD7lI1ivbpTOOzhcSb9wUCNAijdbWQexJWY21vzHP6mLKgTykluWGCKoz25gjSif3psemX8/Es7ZahAQbNjzQ/4OKRJVKtWuuO8DTFbBEJgb2fUQPS/Rb0VhURo33jydtv/sXEMEy5M93d3p4ylVoN7LSyAtWY9WNhBN0btP9+P/YR6zMxCTGPdURQET+kofowOypz3JPEVPUPzjg6gk5riLH6z8cKLL8VvzWbdIY823vYAWPkcWRyjEcceUT/4lCeNIUq5nE79hTYgf/FRKKu+meOuJ+NY5bGdaUKCMGrsbKcEombqCvQ9UMw9uhrfeewBkb30YCEvJv/6Bhz2gT4awBphB2bmOK1VIF9j7TMviCmqmCr78l/jzDzZupLkNx9eHXE7NqEIxEMgtAcp37vbTMFDsipqHP0T48Sct+SaZhZMSr9ZZbSsLUmL2Q1a+fg== X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(376014)(36860700016)(1800799024)(18002099003)(56012099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: osQvFUVY7WpOvhjAQjinlorZjvJK3l1vbbjw1E7DiaT/HXxycxUP04xdhYNzvKw5tFiEyR4CEZWHZDWzDlIsREWdqubTKiK+5sWyiahm4/2xVaBHMez26AS7nIcZn00oInmtBnoYsKtr0Gvn3MyTd9NfOGQ5v/iJwsxIXtzF8O6G1w24aCZwznPnO8MJzgCRDuFUmQLydweWgOZ4ojvOkzNeP4EMKFzNin64g69ycg+3p7Jr2eeusOYBwDbafmUcNKXuASwc+M8p1rkHWKCfaPy8rQ2FkfSWXnoul7ueKQEKaIToHsAT4tWpNXG5rqebcaXaNlOMPDXIpZ0B1qHFlrWFHTOtqlfC/v8vfJDK7LqvSoWhE76xP9poVccSCjbvaCoUi+rdFXLqlmV1H32+sKypmD3fgjRzlkCMxT43ALoXBjsg7SdazJhQKODlru6d X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Apr 2026 23:21:00.0721 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fc0d3098-7dbc-4b22-77db-08de94332a05 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD82.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB6843 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260406_162108_328494_C56ACEBE X-CRM114-Status: GOOD ( 13.38 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The PMCCNTR_EL0 in NVIDIA Olympus CPU may increment while in WFI/WFE, which does not align with counting CPU_CYCLES on a programmable counter. Add a MIDR range entry and refuse PMCCNTR_EL0 for cycle events on affected parts so perf does not mix the two behaviors. Signed-off-by: Besar Wicaksono --- drivers/perf/arm_pmuv3.c | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/drivers/perf/arm_pmuv3.c b/drivers/perf/arm_pmuv3.c index 8014ff766cff..b5d2f60af6f0 100644 --- a/drivers/perf/arm_pmuv3.c +++ b/drivers/perf/arm_pmuv3.c @@ -978,6 +978,29 @@ static int armv8pmu_get_chain_idx(struct pmu_hw_events *cpuc, return -EAGAIN; } +/* + * List of CPUs that should avoid using PMCCNTR_EL0. + */ +static struct midr_range armv8pmu_avoid_pmccntr_cpus[] = { + /* + * The PMCCNTR_EL0 in Olympus CPU may still increment while in WFI/WFE state. + * This is an implementation specific behavior and not an erratum. + * + * From ARM DDI0487 D14.4: + * It is IMPLEMENTATION SPECIFIC whether CPU_CYCLES and PMCCNTR count + * when the PE is in WFI or WFE state, even if the clocks are not stopped. + * + * From ARM DDI0487 D24.5.2: + * All counters are subject to any changes in clock frequency, including + * clock stopping caused by the WFI and WFE instructions. + * This means that it is CONSTRAINED UNPREDICTABLE whether or not + * PMCCNTR_EL0 continues to increment when clocks are stopped by WFI and + * WFE instructions. + */ + MIDR_ALL_VERSIONS(MIDR_NVIDIA_OLYMPUS), + {} +}; + static bool armv8pmu_can_use_pmccntr(struct pmu_hw_events *cpuc, struct perf_event *event) { @@ -1011,6 +1034,14 @@ static bool armv8pmu_can_use_pmccntr(struct pmu_hw_events *cpuc, if (cpu_pmu->has_smt) return false; + /* + * On some CPUs, PMCCNTR_EL0 does not match the behavior of CPU_CYCLES + * programmable counter, so avoid routing cycles through PMCCNTR_EL0 to + * prevent inconsistency in the results. + */ + if (is_midr_in_range_list(armv8pmu_avoid_pmccntr_cpus)) + return false; + return true; } -- 2.43.0