From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 10899EDB7F1 for ; Tue, 7 Apr 2026 10:29:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=Wbf3E557N4SEJDt5I9ywbJWL0cExXrE5XOjT3Zxvn0w=; b=w0GwTjubqlrIaiVyDSqemzj5/7 xSLmD0h7jdjIx548gL7Tk3PMU+kEs0w0C9sYB3TiERYynXsc1jPPEzcd40yemi/qcFddSci+NMfTk BHsiWDircxEgijo/Et9/yxLDotq46ULzntLLmMCsSL7Wyw5rL7onCXuvVNjQa2ae7VKGoC4nX3PIm 15/daXVLg5x/Y/+1m4RjM+zStxlzejRAa+cIpEUqCk2m3ZdH83wwYVBY5n1HyN83/SWTL39hu9RDo aC0mOtYRwZoiCNzOUIRjY3fvwUmWpR/yd04Nm3ARHVmo3ceZV23teJ3jsGr9fcvKDkeHHAHP9s2wg 0PKtlVNA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1wA3g2-00000006Hqo-1WJ2; Tue, 07 Apr 2026 10:28:58 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1wA3fz-00000006Ho4-0djj for linux-arm-kernel@lists.infradead.org; Tue, 07 Apr 2026 10:28:56 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 362271BB2; Tue, 7 Apr 2026 03:28:48 -0700 (PDT) Received: from gaia.lan (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 1FC3C3F641; Tue, 7 Apr 2026 03:28:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1775557733; bh=T6AHbmBi2TmUQfIv141VhNW0xBnK7itHroSBTpypuwo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Gm3Lcl6BH56vlepcWbK3Q8eUrQbMIo7XDVs6HEv4zMecidvXdEkeHr5VQGJEXAoQk bu0MBLbtbjm+tj0cdzcrp+LhDtpvoIFuKklQW4Hr7nLogxmXyFCaOVQUErRUaRAz17 gkyrJN3mNxJgY4W1ypd0Ypt+nuH6sAakH6tena30= From: Catalin Marinas To: linux-arm-kernel@lists.infradead.org Cc: Will Deacon , James Morse , Mark Rutland , Mark Brown Subject: [PATCH v5 3/4] arm64: cputype: Add C1-Pro definitions Date: Tue, 7 Apr 2026 11:28:43 +0100 Message-ID: <20260407102848.2266988-4-catalin.marinas@arm.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260407102848.2266988-1-catalin.marinas@arm.com> References: <20260407102848.2266988-1-catalin.marinas@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260407_032855_224361_435F69B5 X-CRM114-Status: UNSURE ( 9.83 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add cputype definitions for C1-Pro. These will be used for errata detection in subsequent patches. These values can be found in "Table A-303: MIDR_EL1 bit descriptions" in issue 07 of the C1-Pro TRM: https://documentation-service.arm.com/static/6930126730f8f55a656570af Signed-off-by: Catalin Marinas Acked-by: Mark Rutland Cc: Will Deacon Cc: James Morse --- arch/arm64/include/asm/cputype.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h index 08860d482e60..7b518e81dd15 100644 --- a/arch/arm64/include/asm/cputype.h +++ b/arch/arm64/include/asm/cputype.h @@ -98,6 +98,7 @@ #define ARM_CPU_PART_CORTEX_A725 0xD87 #define ARM_CPU_PART_CORTEX_A720AE 0xD89 #define ARM_CPU_PART_NEOVERSE_N3 0xD8E +#define ARM_CPU_PART_C1_PRO 0xD8B #define APM_CPU_PART_XGENE 0x000 #define APM_CPU_VAR_POTENZA 0x00 @@ -189,6 +190,7 @@ #define MIDR_CORTEX_A725 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A725) #define MIDR_CORTEX_A720AE MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A720AE) #define MIDR_NEOVERSE_N3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N3) +#define MIDR_C1_PRO MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_C1_PRO) #define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX) #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX) #define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX)