[PATCH v4 10/10] iommu/arm-smmu-v3: Allow sharing domain across SMMUs

Nicolin Chen
2026-03-19T19:53:13Z

VMM needs a domain holding the mappings between gPA to hPA. It can be an S1
domain or an S2 nesting parent domain, depending on whether the VM is built
with a vSMMU or not.

Given that the IOAS for this gPA mapping is the same across SMMU instances,
this domain can be shared across devices even if they sit behind different
SMMUs, so long as the underlying page table is compatible between the SMMU
instances.

There is no direct information about the page table from the master device,
but a comparison can be done between the page table bits held in the domain
and the SMMU feature bits that are used to decide those page table bits.

Replace the smmu test in arm_smmu_attach_dev() and arm_vsmmu_init() with a
compatibility test for the S1 and S2 cases respectively.

Signed-off-by: Nicolin Chen <nicolinc@nvidia.com>
---
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 27 +++++++++++++++++++
.../arm/arm-smmu-v3/arm-smmu-v3-iommufd.c | 2 +-
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 3 +--
3 files changed, 29 insertions(+), 3 deletions(-)

diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
index e0da09a2cc07c..81fb74bf589b3 100644
--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
@@ -9,6 +9,7 @@
#define _ARM_SMMU_V3_H

#include <linux/bitfield.h>
+#include <linux/io-pgtable.h>
#include <linux/iommu.h>
#include <linux/iommufd.h>
#include <linux/kernel.h>
@@ -987,6 +988,32 @@ struct arm_smmu_nested_domain {
__le64 ste[2];
};

+static inline bool
+arm_smmu_domain_can_share(struct arm_smmu_domain *smmu_domain,
+ struct arm_smmu_device *new_smmu)
+{
+ struct io_pgtable *pgtbl =
+ io_pgtable_ops_to_pgtable(smmu_domain->pgtbl_ops);
+
+ if (pgtbl->fmt == ARM_64_LPAE_S1 &&
+ !(new_smmu->features & ARM_SMMU_FEAT_TRANS_S1))
+ return false;
+ if (pgtbl->fmt == ARM_64_LPAE_S2 &&
+ !(new_smmu->features & ARM_SMMU_FEAT_TRANS_S2))
+ return false;
+ if (pgtbl->cfg.pgsize_bitmap & ~new_smmu->pgsize_bitmap)
+ return false;
+ if (pgtbl->cfg.oas > new_smmu->oas)
+ return false;
+ if (pgtbl->cfg.coherent_walk &&
+ !(new_smmu->features & ARM_SMMU_FEAT_COHERENCY))
+ return false;
+ if ((pgtbl->cfg.quirks & IO_PGTABLE_QUIRK_ARM_S2FWB) &&
+ !(new_smmu->features & ARM_SMMU_FEAT_S2FWB))
+ return false;
+ return true;
+}
+
/* The following are exposed for testing purposes. */
struct arm_smmu_entry_writer_ops;
struct arm_smmu_entry_writer {
diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c
index d17f8cb423b0c..883ca020ee87b 100644
--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c
+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c
@@ -470,7 +470,7 @@ int arm_vsmmu_init(struct iommufd_viommu *viommu,
struct arm_smmu_domain *s2_parent = to_smmu_domain(parent_domain);
int id, ret;

- if (s2_parent->smmu != smmu)
+ if (!arm_smmu_domain_can_share(s2_parent, smmu))
return -EINVAL;

id = ida_alloc_range(&smmu->vmid_map, 1, (1 << smmu->vmid_bits) - 1,
diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
index ea288b6f39ff8..b1d22668e3162 100644
--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
@@ -16,7 +16,6 @@
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/interrupt.h>
-#include <linux/io-pgtable.h>
#include <linux/iopoll.h>
#include <linux/module.h>
#include <linux/msi.h>
@@ -3714,7 +3713,7 @@ static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev,
state.master = master = dev_iommu_priv_get(dev);
smmu = master->smmu;

- if (smmu_domain->smmu != smmu)
+ if (!arm_smmu_domain_can_share(smmu_domain, smmu))
return -EINVAL;

if (smmu_domain->stage == ARM_SMMU_DOMAIN_S1) {
--
2.43.0