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Fri, 10 Apr 2026 17:16:25 +0000 (GMT) Received: from p1lg14885.dc01.its.hpecorp.net (unknown [10.119.18.236]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by p1lg14880.it.hpe.com (Postfix) with ESMTPS id B58DE801AC7; Fri, 10 Apr 2026 17:16:24 +0000 (UTC) Received: from hpe.com (unknown [16.231.227.36]) by p1lg14885.dc01.its.hpecorp.net (Postfix) with ESMTP id 47C3D808530; Fri, 10 Apr 2026 17:16:24 +0000 (UTC) From: nick.hawkins@hpe.com To: catalin.marinas@arm.com, will@kernel.org Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, krzysztof.kozlowski@oss.qualcomm.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Nick Hawkins Subject: [PATCH v5 3/4] arm64: dts: hpe: Add HPE GSC SoC and DL340 Gen12 board DTS Date: Fri, 10 Apr 2026 17:16:10 +0000 Message-ID: <20260410171611.2547255-4-nick.hawkins@hpe.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260410171611.2547255-1-nick.hawkins@hpe.com> References: <20260410171611.2547255-1-nick.hawkins@hpe.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDEwMDE2MiBTYWx0ZWRfX0BAOoDBxs6sA r0F7LzMujNk8BmAclWXfGTlNcbIhvpvrej/P5XnNHt3Dxrm12IUHXY0hn6Rosq7BNkJI2GBVaya wzj/Mv8BIHNCVU8QDVpFg3mm4lpZBskTIGnQapjXb3i3lHLTSE4JOCwcg0gUzg9fL8v3TUOL5jR TNU4/OzUqO9/4n4Euj57hlIOrQW90ioQeE/JmNcQ2sMgibdCVKMnn1lJTk+qMHk0NJXOEx/e1rS Yl2e346uQiAJLivY27nxekPLBAZa60feNsTWNZZtuR3W8331tA2A8ucjzbhcg3Tdmu7ICmp8gVX cVJR63Ah/dS4QgZ916qIbQ7n5Vnqmhu288PXr5UpCHiMOOCOyCKlDifLWRt64DYkjFwyBm/WC0Q yMF7FGaL8Lse6Yv4VeobnYmfkJXd+dUVb5xNujq9EcNX7pKb3gnX2O9AzJenY0/C9Bye5OoVts/ I+pBUseFqnQnJOiPhSg== X-Proofpoint-ORIG-GUID: N05lh3INzBHd0J60Twa_1S2imvFuuJ4J X-Proofpoint-GUID: N05lh3INzBHd0J60Twa_1S2imvFuuJ4J X-Authority-Analysis: v=2.4 cv=At7eGu9P c=1 sm=1 tr=0 ts=69d93069 cx=c_pps a=A+SOMQ4XYIH4HgQ50p3F5Q==:117 a=A+SOMQ4XYIH4HgQ50p3F5Q==:17 a=A5OVakUREuEA:10 a=VkNPw1HP01LnGYTKEx00:22 a=gQcMVamqm3wCPoSYhaRC:22 a=RtSn8ETxjE2H05FtM2s8:22 a=MvuuwTCpAAAA:8 a=KK1IH8HFS8MDNeiM4vUA:9 X-HPE-SCL: -1 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-10_05,2026-04-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 impostorscore=0 suspectscore=0 phishscore=0 lowpriorityscore=0 clxscore=1015 spamscore=0 priorityscore=1501 adultscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604010000 definitions=main-2604100162 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260410_101633_200498_CF7FF4FC X-CRM114-Status: GOOD ( 15.14 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Nick Hawkins Add SoC-level DTSI for the HPE GSC ARM64 BMC SoC, covering the CPU cluster, GIC v3 interrupt controller, ARM64 generic timer, and console UART. Add the board-level DTS for the HPE DL340 Gen12, which includes gsc.dtsi and adds memory and chosen nodes. Signed-off-by: Nick Hawkins --- arch/arm64/boot/dts/hpe/Makefile | 2 + arch/arm64/boot/dts/hpe/gsc-dl340gen12.dts | 18 ++++ arch/arm64/boot/dts/hpe/gsc.dtsi | 104 +++++++++++++++++++++ 3 files changed, 124 insertions(+) create mode 100644 arch/arm64/boot/dts/hpe/Makefile create mode 100644 arch/arm64/boot/dts/hpe/gsc-dl340gen12.dts create mode 100644 arch/arm64/boot/dts/hpe/gsc.dtsi diff --git a/arch/arm64/boot/dts/hpe/Makefile b/arch/arm64/boot/dts/hpe/Makefile new file mode 100644 index 000000000000..6b547b8a8154 --- /dev/null +++ b/arch/arm64/boot/dts/hpe/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0-only +dtb-$(CONFIG_ARCH_HPE) += gsc-dl340gen12.dtb diff --git a/arch/arm64/boot/dts/hpe/gsc-dl340gen12.dts b/arch/arm64/boot/dts/hpe/gsc-dl340gen12.dts new file mode 100644 index 000000000000..7a3d9f1c4b2e --- /dev/null +++ b/arch/arm64/boot/dts/hpe/gsc-dl340gen12.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "gsc.dtsi" + +/ { + compatible = "hpe,gsc-dl340gen12", "hpe,gsc"; + model = "HPE ProLiant DL340 Gen12"; + + chosen { + stdout-path = &uartc; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x40000000>; + }; +}; diff --git a/arch/arm64/boot/dts/hpe/gsc.dtsi b/arch/arm64/boot/dts/hpe/gsc.dtsi new file mode 100644 index 000000000000..1f4c2a7b3d91 --- /dev/null +++ b/arch/arm64/boot/dts/hpe/gsc.dtsi @@ -0,0 +1,104 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree file for HPE GSC + */ + +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + + osc: clock-33333333 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-output-names = "osc"; + clock-frequency = <33333333>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0>; + enable-method = "spin-table"; + cpu-release-addr = <0 0xa0008048>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <1>; + enable-method = "spin-table"; + cpu-release-addr = <0 0xa0008048>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + }; + + soc: soc@80000000 { + compatible = "simple-bus"; + reg = <0x80000000 0x80000000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + uarta: serial@c00000e0 { + compatible = "ns16550a"; + reg = <0xc00000e0 0x8>; + clock-frequency = <1846153>; + interrupt-parent = <&gic>; + interrupts = ; + reg-shift = <0>; + }; + + uartb: serial@c00000e8 { + compatible = "ns16550a"; + reg = <0xc00000e8 0x8>; + clock-frequency = <1846153>; + interrupt-parent = <&gic>; + interrupts = ; + reg-shift = <0>; + }; + + uartc: serial@c00000f0 { + compatible = "ns16550a"; + reg = <0xc00000f0 0x8>; + clock-frequency = <1846153>; + interrupt-parent = <&gic>; + interrupts = ; + reg-shift = <0>; + }; + + uarte: serial@c00003e0 { + compatible = "ns16550a"; + reg = <0xc00003e0 0x8>; + clock-frequency = <1846153>; + interrupt-parent = <&gic>; + interrupts = ; + reg-shift = <0>; + }; + + gic: gic@ce000000 { + compatible = "arm,gic-v3"; + reg = <0xce000000 0x10000>, + <0xce060000 0x40000>, + <0xce200000 0x40000>; + #address-cells = <0>; + #interrupt-cells = <3>; + #redistributor-regions = <1>; + interrupt-controller; + redistributor-stride = <0x0 0x20000>; + }; + }; +}; -- 2.34.1