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Sat, 11 Apr 2026 05:28:22 -0700 (PDT) Received: from udknight.localhost ([240e:379:1ea4:201:1d74:bf36:51db:2590]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2b2d4f0ada5sm62470315ad.42.2026.04.11.05.28.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 11 Apr 2026 05:28:21 -0700 (PDT) Received: from udknight.localhost (localhost [127.0.0.1]) by udknight.localhost (8.14.9/8.14.4) with ESMTP id 63BCS4Va011166; Sat, 11 Apr 2026 20:28:05 +0800 Received: (from root@localhost) by udknight.localhost (8.14.9/8.14.9/Submit) id 63BCRtY1011157; Sat, 11 Apr 2026 20:27:55 +0800 Date: Sat, 11 Apr 2026 20:27:55 +0800 From: Wang YanQing To: "Russell King (Oracle)" , akpm@linux-foundation.org, willy@infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2] arm: lpae: fix non-atomic page table entry update issue Message-ID: <20260411122755.GA3274@udknight> Mail-Followup-To: Wang YanQing , "Russell King (Oracle)" , akpm@linux-foundation.org, willy@infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org References: <20260315004746.GA32062@udknight> <20260315032950.GA5618@udknight> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260315032950.GA5618@udknight> User-Agent: Mutt/1.7.1 (2016-10-04) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260411_052823_619081_6ECDB57F X-CRM114-Status: GOOD ( 24.72 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Sun, Mar 15, 2026 at 11:29:50AM +0800, Wang YanQing wrote: > On Sun, Mar 15, 2026 at 01:12:28AM +0000, Russell King (Oracle) wrote: > > On Sun, Mar 15, 2026 at 08:47:46AM +0800, Wang YanQing wrote: > > Thanks. Now, please locate where the need for the updates to the page > > tables needs to be done atomically, bearing in mind that we program > > SCTLR.AFE=1 and SCTLR.HA=0, meaning the hardware won't write-back to > > the page tables to e.g. update the access flag. > > When LPAE is enabled and in the 3G/1G userspace & kernel space config, we > use ttbr0 for address space 0-3G, and use ttbr1 for top 1G kernel space, > but wait a moment, the module space is in ttbr0 instead of ttbr1, because > module space is belong to 0-3G. > > Then we don't switch ttbr0 to the same value as ttbr1 in task switch, so > when we switch from normal userspace thread to kernel thread, we use the > do_translation_fault() to fault in the module space for the kernel thread > when it accesses the module space. Now please think a situation that > userspace repeats create new short-lived processes (run shell cmds, etc), > we will use do_translation_fault() to fault in the PMD entries repeatly > when switch from new created process to running kernel thread, we need > to update pmd entry automatically here, hw is allowed to do data/instruction > preload and trigger page table walker to see the partial update pmd entry, > page table walker will cache it, and it will cause translation fault, > because it doesn't see the upper 32-bit. > > When the userspace process is a multi-threads process, in smp environment, > other cpus could use the same pgd for their according kernel thread, all > the page table walker of the smp cpus have the chance to cache the partial > update entry. > Hi Russell King, what is the status about this patch? On some SoC, Texas Instruments Keystone etc, it will run arm32 linux kernel on high address (KEYSTONE_HIGH_PHYS_START = 0x800000000ULL), then all the physical address of page table will be 64-bit and will meet the issue described in the patch Thanks