From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 24833F8E4B6 for ; Fri, 17 Apr 2026 07:35:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=iXLfij59esBh5ZfuMnm2qRzffXK1qeBPCgD8+QKvanI=; b=TaxJqIjWowqVFj9RMuYOd1AW7n nhI213lpDfQnjoe8UsAAx/HhMuc32JX6crpIk6YLNZZRzCJzmDxPS6AwbKNSHFld39CnNYXSFMAb4 gMDTAOuhcb+e/r0kDstYpYZKQo832q/QfsUct2yaSDtR3vmSediz6WsZz3KKJi6gbXekSbvj94XTF VFWofbmn2XDrzYZloB8+4dOf2it7J7dY9FGMFAUxdbtYTTg5PWte/7CRDIHgBiBeYIXKyTlN+pOVc Ikb+c2T+aUQzLstbmbTWNCaZP3mHcu/FjBf68VP79wrd5TlS8YJkDBeFAygVers88MkYGkxmvuwgK fJrVkWyA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1wDdjK-00000003atC-2nNz; Fri, 17 Apr 2026 07:35:10 +0000 Received: from mx0a-0031df01.pphosted.com ([205.220.168.131]) by bombadil.infradead.org with esmtps (Exim 4.98.2 #2 (Red Hat Linux)) id 1wDdjI-00000003as8-2NJJ for linux-arm-kernel@lists.infradead.org; Fri, 17 Apr 2026 07:35:09 +0000 Received: from pps.filterd (m0279865.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 63H0fwNP869558 for ; Fri, 17 Apr 2026 07:35:08 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=qcppdkim1; bh=iXLfij59esB h5ZfuMnm2qRzffXK1qeBPCgD8+QKvanI=; b=p4vZ+yDepnrhkid1mH8wq2W96Lc E4nmvIwkQQMHelka0rBQe5GNlL6uBvFPCJfLTc0JZwoM/Y654c6NWcOV7eYsjhN7 0eL7eXpp3ypr/mt/cE8ItfSc7GqmvREbw6s6dEs0Qo9zqpC4futMw9T33ucKl/M7 b415xMoIhBaTpZr0sQ/MOPHjljnAOgbSbDU+TMmCe1n7ucOsQGYiH3r0CY9B3UXr iuQRRkFcBykh4r1GYIwjttOgD3UWmw/Fp185U9zoDIxfMFrWznJDpl9DhzEvK+iQ r/iFznbiX9NhKGS3d5m/wK8zRYiSqmNEQMbMkcVrSlyL2bKVFYycv0nqskQ== Received: from mail-dy1-f200.google.com (mail-dy1-f200.google.com [74.125.82.200]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4djvruc87d-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Fri, 17 Apr 2026 07:35:07 +0000 (GMT) Received: by mail-dy1-f200.google.com with SMTP id 5a478bee46e88-2c0ba59a830so597694eec.0 for ; Fri, 17 Apr 2026 00:35:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1776411244; x=1777016044; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=iXLfij59esBh5ZfuMnm2qRzffXK1qeBPCgD8+QKvanI=; b=UMRyCbK8cAQamY5wbIGXgYNffbNyRxFAbKfeAXpNSTCa7jtsYLUAh98aaXsT+jGKdp ydhw95PEGx1go/JbLBX9yfg42jBauylnFWBCE2Rg/eaUwr2vAwFZtWp5+P4qg3MiZZ4b 3qbMb/TzRcTUNXh0lPnPgbXxWRZisoo9OykmMNAq6sjE4O8dB0Pr2K/6xYxJELHt16LC IkhfLjmQq9lrj31M99ywqvm/qCo1UaRpvWAcdrqT5TmKK45KNI03ffjwReBUl1w+Lz9M Q/Qzi1gTc+xMo1+BCctvypzd5SVl/DECj/+OBogUA05183wtTCYNTOqOE9a4fQRMrtbB Xfrw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1776411244; x=1777016044; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=iXLfij59esBh5ZfuMnm2qRzffXK1qeBPCgD8+QKvanI=; b=EAHVXl3OPL4XyDRTivf3Y7IGxUczjc7Rc96grJfqtF/96CFnBKcANi4lZROAGVB7An GF8eEg9ZiZbSLaLHaFV1O5l4cMcJ+l1EnI+KCi8THig3KtteF8Wai4ZQgiNDFWyEAdvS xuD4jN5wf3OBqgQMpL+x0qNRRZ0WBTgkN0TP43hJzEeaON7diJH5vpR2ytUwguc+qgO4 e2QOFmJ1qb65D2weV9ub8RXMdpuOB/pAvtuCqnx4UxdNQuguLGf/6ja6CUYjcyOkYmFG 7xb7b+gy0+FC+KHEfgyYoplT+w8EW8vAUZhcypzEZcj8+vrSJPySJEvV8CDYKA3FdTo2 6g0Q== X-Forwarded-Encrypted: i=1; AFNElJ8A2DlyZwSDf0U4vG6t+KpuUdiuV0ICj0jKcfmM4wPa/v/yTvViTV7+rWwF0fJVY1TnR35KAy9m3/MvFp3XCyKK@lists.infradead.org X-Gm-Message-State: AOJu0Yxc90Rxv2ms7onVumcepyOXN0J/UGDylNBP54ltqXlvVOw/mH4/ +QCxsEKGFHPQQVbLUZuClY9WaFsShEtd+j5Jyf2uljUjs1PBr0Ncg1wLhbJa5Ynd49hwzZKYnn/ tgNBCBxoCgbmfI9ilPR01vJu2Gkv2spSpJBNHBuh4mflMJOlzCnjiiQby+DvvrGErrH7LZcCAvh NXQw== X-Gm-Gg: AeBDiesQCxnd08NatXAvqXauORWm78sku895cBnW0z8TB3wtDFpZsYkShzSvt/5+bwK 0axk+2/67OUFQP4Li05STJ6AYfDlcGjmA8PeZM/Qbm6qNVwo+fDACI15qH4WBKIJEjRGqR2GNJI xKwWIJa2Ndy3v5atSQHm7k8PqTZaT23OJeYcw+1pcwp8sXbOUuwhqFFDBPDF+XMT3rVCGKTuRkl T696ME6aesC6/VjeWDjKU0FNBewNjPKHekYsQNgrfVKTWJ2zAyN/Y0QvBzWT6twxCRqYk/E7TdL qtRdm29aEUM9aP6AMzYh4dqKFGGMhVc9qymOM8xojekjBuCY6wNc4BYECDSU7xIOsEULt0y0HJY zRsYsQ0vNZptK8RPgu5hgFv0pjfkJqAKLwzu//lkDgubtUPeNVPIlO7UNA4JvOGvkdobQjMJk+S DFHrc7kPGxaWY= X-Received: by 2002:a05:7300:7491:b0:2b7:38cf:c2fd with SMTP id 5a478bee46e88-2e4873f1afemr748089eec.26.1776411243908; Fri, 17 Apr 2026 00:34:03 -0700 (PDT) X-Received: by 2002:a05:7300:7491:b0:2b7:38cf:c2fd with SMTP id 5a478bee46e88-2e4873f1afemr748072eec.26.1776411243240; Fri, 17 Apr 2026 00:34:03 -0700 (PDT) Received: from hu-songchai-lv.qualcomm.com (Global_NAT1.qualcomm.com. [129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2e53ccd2564sm1135168eec.18.2026.04.17.00.34.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Apr 2026 00:34:02 -0700 (PDT) From: Songwei Chai To: andersson@kernel.org, alexander.shishkin@linux.intel.com, mike.leach@linaro.org, konrad.dybcio@oss.qualcomm.com, suzuki.poulose@arm.com, james.clark@arm.com, krzk+dt@kernel.org, conor+dt@kernel.org Cc: Songwei Chai , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, coresight@lists.linaro.org, devicetree@vger.kernel.org, gregkh@linuxfoundation.org, Jie Gan Subject: [PATCH v14 3/7] qcom-tgu: Add signal priority support Date: Fri, 17 Apr 2026 00:33:32 -0700 Message-Id: <20260417073336.2712426-4-songwei.chai@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260417073336.2712426-1-songwei.chai@oss.qualcomm.com> References: <20260417073336.2712426-1-songwei.chai@oss.qualcomm.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDE3MDA3NCBTYWx0ZWRfX7iewPhm7Xvr/ B87wxaEU6REZhsKSusokY9rBjHOcgyfRVKjHPpQrG8cCbmLNKGUY3JEmrLBtuzmRrHgFRjg4DeW nzv8C6SmuqJD4riZo+H3Y6D4SmmazitlOgU7AW0Oel/xUC7zYS9opCxrfxdyO8TZ3HkIyacGwuc uU5WcwY3MlyZ5eYWSoT5qRrPXbZUC9QxQbEfXWXCjBAj3SGOck5I2aE9v0E7fxdRSFL7+HP9V6y hxQ7+bO9PbFpNkaFhySTrndKARujQcOkAyt898y8S2sm4GhIcbvN9svB+Fja0D4ipeVRE7VBOER nW3hIWn85++kmWXueZlh7n+V8QWeJamtq8f3OBf5miO87FU2BBRosHCjSYsyNMbVv3FJEkzwkM7 auqP0GhJvz+s+NupG0Zo5zNPJ4u+cUPKMu/g/bhnODprEBEnJ9///NB2a6ceFLkXYZ8yp3UvrUO KS8B7epl9Rjg8FbQAVw== X-Proofpoint-GUID: nSIOsz7RApb6qt4-x_exrX8k9gwaakCH X-Proofpoint-ORIG-GUID: nSIOsz7RApb6qt4-x_exrX8k9gwaakCH X-Authority-Analysis: v=2.4 cv=GcInWwXL c=1 sm=1 tr=0 ts=69e1e2ab cx=c_pps a=PfFC4Oe2JQzmKTvty2cRDw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=EUspDBNiAAAA:8 a=aHbVEu0FunmFpxPyS6YA:9 a=6Ab_bkdmUrQuMsNx7PHu:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-16_04,2026-04-16_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 adultscore=0 priorityscore=1501 malwarescore=0 impostorscore=0 phishscore=0 suspectscore=0 bulkscore=0 spamscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604070000 definitions=main-2604170074 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260417_003508_617159_4CFFD16B X-CRM114-Status: GOOD ( 20.28 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Like circuit of a Logic analyzer, in TGU, the requirement could be configured in each step and the trigger will be created once the requirements are met. Add priority functionality here to sort the signals into different priorities. The signal which is wanted could be configured in each step's priority node, the larger number means the higher priority and the signal with higher priority will be sensed more preferentially. Reviewed-by: Jie Gan Signed-off-by: Songwei Chai --- .../ABI/testing/sysfs-bus-amba-devices-tgu | 7 + drivers/hwtracing/qcom/tgu.c | 161 ++++++++++++++++++ drivers/hwtracing/qcom/tgu.h | 114 +++++++++++++ 3 files changed, 282 insertions(+) diff --git a/Documentation/ABI/testing/sysfs-bus-amba-devices-tgu b/Documentation/ABI/testing/sysfs-bus-amba-devices-tgu index f877a00fcaa5..223873789ca6 100644 --- a/Documentation/ABI/testing/sysfs-bus-amba-devices-tgu +++ b/Documentation/ABI/testing/sysfs-bus-amba-devices-tgu @@ -7,3 +7,10 @@ Description: Accepts only one of the 2 values - 0 or 1. 0 : disable TGU. 1 : enable TGU. + +What: /sys/bus/amba/devices//step[0:7]_priority[0:3]/reg[0:17] +Date: April 2026 +KernelVersion: 7.1 +Contact: Jinlong Mao , Songwei Chai +Description: + (RW) Set/Get the sensed signal with specific step and priority for TGU. diff --git a/drivers/hwtracing/qcom/tgu.c b/drivers/hwtracing/qcom/tgu.c index 49c8f710b931..7d69986c3e3d 100644 --- a/drivers/hwtracing/qcom/tgu.c +++ b/drivers/hwtracing/qcom/tgu.c @@ -14,14 +14,123 @@ #include "tgu.h" +static int calculate_array_location(struct tgu_drvdata *drvdata, + int step_index, int operation_index, + int reg_index) +{ + return operation_index * (drvdata->num_step) * (drvdata->num_reg) + + step_index * (drvdata->num_reg) + reg_index; +} + +static ssize_t tgu_dataset_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct tgu_drvdata *drvdata = dev_get_drvdata(dev); + struct tgu_attribute *tgu_attr = + container_of(attr, struct tgu_attribute, attr); + int index; + + index = calculate_array_location(drvdata, tgu_attr->step_index, + tgu_attr->operation_index, + tgu_attr->reg_num); + + return sysfs_emit(buf, "0x%x\n", + drvdata->value_table->priority[index]); +} + +static ssize_t tgu_dataset_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + struct tgu_drvdata *tgu_drvdata = dev_get_drvdata(dev); + struct tgu_attribute *tgu_attr = + container_of(attr, struct tgu_attribute, attr); + unsigned long val; + int index; + int ret; + + ret = kstrtoul(buf, 0, &val); + if (ret) + return ret; + + guard(spinlock)(&tgu_drvdata->lock); + index = calculate_array_location(tgu_drvdata, tgu_attr->step_index, + tgu_attr->operation_index, + tgu_attr->reg_num); + + tgu_drvdata->value_table->priority[index] = val; + + return size; +} + +static umode_t tgu_node_visible(struct kobject *kobject, + struct attribute *attr, + int n) +{ + struct device *dev = kobj_to_dev(kobject); + struct tgu_drvdata *drvdata = dev_get_drvdata(dev); + struct device_attribute *dev_attr = + container_of(attr, struct device_attribute, attr); + struct tgu_attribute *tgu_attr = + container_of(dev_attr, struct tgu_attribute, attr); + + if (tgu_attr->step_index >= drvdata->num_step) + return SYSFS_GROUP_INVISIBLE; + + if (tgu_attr->reg_num >= drvdata->num_reg) + return 0; + + return attr->mode; +} + static void tgu_write_all_hw_regs(struct tgu_drvdata *drvdata) { + int i, j, k, index; + TGU_UNLOCK(drvdata->base); + for (i = 0; i < drvdata->num_step; i++) { + for (j = 0; j < MAX_PRIORITY; j++) { + for (k = 0; k < drvdata->num_reg; k++) { + index = calculate_array_location( + drvdata, i, j, k); + + writel(drvdata->value_table->priority[index], + drvdata->base + + PRIORITY_REG_STEP(i, j, k)); + } + } + } /* Enable TGU to program the triggers */ writel(1, drvdata->base + TGU_CONTROL); TGU_LOCK(drvdata->base); } +static void tgu_set_reg_number(struct tgu_drvdata *drvdata) +{ + int num_sense_input; + int num_reg; + u32 devid; + + devid = readl(drvdata->base + TGU_DEVID); + + num_sense_input = TGU_DEVID_SENSE_INPUT(devid); + num_reg = (num_sense_input * TGU_BITS_PER_SIGNAL) / LENGTH_REGISTER; + + if ((num_sense_input * TGU_BITS_PER_SIGNAL) % LENGTH_REGISTER) + num_reg++; + + drvdata->num_reg = num_reg; +} + +static void tgu_set_steps(struct tgu_drvdata *drvdata) +{ + u32 devid; + + devid = readl(drvdata->base + TGU_DEVID); + + drvdata->num_step = TGU_DEVID_STEPS(devid); +} + static int tgu_enable(struct device *dev) { struct tgu_drvdata *drvdata = dev_get_drvdata(dev); @@ -121,6 +230,38 @@ static const struct attribute_group tgu_common_grp = { static const struct attribute_group *tgu_attr_groups[] = { &tgu_common_grp, + PRIORITY_ATTRIBUTE_GROUP_INIT(0, 0), + PRIORITY_ATTRIBUTE_GROUP_INIT(0, 1), + PRIORITY_ATTRIBUTE_GROUP_INIT(0, 2), + PRIORITY_ATTRIBUTE_GROUP_INIT(0, 3), + PRIORITY_ATTRIBUTE_GROUP_INIT(1, 0), + PRIORITY_ATTRIBUTE_GROUP_INIT(1, 1), + PRIORITY_ATTRIBUTE_GROUP_INIT(1, 2), + PRIORITY_ATTRIBUTE_GROUP_INIT(1, 3), + PRIORITY_ATTRIBUTE_GROUP_INIT(2, 0), + PRIORITY_ATTRIBUTE_GROUP_INIT(2, 1), + PRIORITY_ATTRIBUTE_GROUP_INIT(2, 2), + PRIORITY_ATTRIBUTE_GROUP_INIT(2, 3), + PRIORITY_ATTRIBUTE_GROUP_INIT(3, 0), + PRIORITY_ATTRIBUTE_GROUP_INIT(3, 1), + PRIORITY_ATTRIBUTE_GROUP_INIT(3, 2), + PRIORITY_ATTRIBUTE_GROUP_INIT(3, 3), + PRIORITY_ATTRIBUTE_GROUP_INIT(4, 0), + PRIORITY_ATTRIBUTE_GROUP_INIT(4, 1), + PRIORITY_ATTRIBUTE_GROUP_INIT(4, 2), + PRIORITY_ATTRIBUTE_GROUP_INIT(4, 3), + PRIORITY_ATTRIBUTE_GROUP_INIT(5, 0), + PRIORITY_ATTRIBUTE_GROUP_INIT(5, 1), + PRIORITY_ATTRIBUTE_GROUP_INIT(5, 2), + PRIORITY_ATTRIBUTE_GROUP_INIT(5, 3), + PRIORITY_ATTRIBUTE_GROUP_INIT(6, 0), + PRIORITY_ATTRIBUTE_GROUP_INIT(6, 1), + PRIORITY_ATTRIBUTE_GROUP_INIT(6, 2), + PRIORITY_ATTRIBUTE_GROUP_INIT(6, 3), + PRIORITY_ATTRIBUTE_GROUP_INIT(7, 0), + PRIORITY_ATTRIBUTE_GROUP_INIT(7, 1), + PRIORITY_ATTRIBUTE_GROUP_INIT(7, 2), + PRIORITY_ATTRIBUTE_GROUP_INIT(7, 3), NULL, }; @@ -128,6 +269,8 @@ static int tgu_probe(struct amba_device *adev, const struct amba_id *id) { struct device *dev = &adev->dev; struct tgu_drvdata *drvdata; + unsigned int *priority; + size_t priority_size; int ret; drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); @@ -143,12 +286,30 @@ static int tgu_probe(struct amba_device *adev, const struct amba_id *id) spin_lock_init(&drvdata->lock); + tgu_set_reg_number(drvdata); + tgu_set_steps(drvdata); + ret = sysfs_create_groups(&dev->kobj, tgu_attr_groups); if (ret) { dev_err(dev, "failed to create sysfs groups: %d\n", ret); return ret; } + drvdata->value_table = + devm_kzalloc(dev, sizeof(*drvdata->value_table), GFP_KERNEL); + if (!drvdata->value_table) + return -ENOMEM; + + priority_size = MAX_PRIORITY * drvdata->num_reg * drvdata->num_step; + + priority = devm_kcalloc(dev, priority_size, + sizeof(*drvdata->value_table->priority), + GFP_KERNEL); + if (!priority) + return -ENOMEM; + + drvdata->value_table->priority = priority; + drvdata->enabled = false; pm_runtime_put(&adev->dev); diff --git a/drivers/hwtracing/qcom/tgu.h b/drivers/hwtracing/qcom/tgu.h index dd7533b9d735..f994d83acb1d 100644 --- a/drivers/hwtracing/qcom/tgu.h +++ b/drivers/hwtracing/qcom/tgu.h @@ -10,6 +10,114 @@ #define TGU_CONTROL 0x0000 #define TGU_LAR 0xfb0 #define TGU_UNLOCK_OFFSET 0xc5acce55 +#define TGU_DEVID 0xfc8 + +#define TGU_DEVID_SENSE_INPUT(devid_val) \ + ((int)FIELD_GET(GENMASK(17, 10), devid_val)) +#define TGU_DEVID_STEPS(devid_val) \ + ((int)FIELD_GET(GENMASK(6, 3), devid_val)) +#define TGU_BITS_PER_SIGNAL 4 +#define LENGTH_REGISTER 32 + +/* + * TGU configuration space Step configuration + * offset table space layout + * x-------------------------x$ x-------------x$ + * | |$ | |$ + * | | | reserve |$ + * | | | |$ + * |coresight management | |-------------|base+n*0x1D8+0x1F4$ + * | registers | |---> |priority[3] |$ + * | | | |-------------|base+n*0x1D8+0x194$ + * | | | |priority[2] |$ + * |-------------------------| | |-------------|base+n*0x1D8+0x134$ + * | | | |priority[1] |$ + * | step[7] | | |-------------|base+n*0x1D8+0xD4$ + * |-------------------------|->base+0x40+7*0x1D8 | |priority[0] |$ + * | | | |-------------|base+n*0x1D8+0x74$ + * | ... | | | condition |$ + * | | | | select |$ + * |-------------------------|->base+0x40+1*0x1D8 | |-------------|base+n*0x1D8+0x60$ + * | | | | condition |$ + * | step[0] |--------------------> | decode |$ + * |-------------------------|-> base+0x40 |-------------|base+n*0x1D8+0x50$ + * | | | |$ + * | Control and status space| |Timer/Counter|$ + * | space | | |$ + * x-------------------------x->base x-------------x base+n*0x1D8+0x40$ + * + */ +#define STEP_OFFSET 0x1D8 +#define PRIORITY_START_OFFSET 0x0074 +#define PRIORITY_OFFSET 0x60 +#define REG_OFFSET 0x4 + +/* Calculate compare step addresses */ +#define PRIORITY_REG_STEP(step, priority, reg)\ + (PRIORITY_START_OFFSET + PRIORITY_OFFSET * priority +\ + REG_OFFSET * reg + STEP_OFFSET * step) + +#define tgu_dataset_rw(name, step_index, type, reg_num) \ + (&((struct tgu_attribute[]){ { \ + __ATTR(name, 0644, tgu_dataset_show, tgu_dataset_store), \ + step_index, \ + type, \ + reg_num, \ + } })[0].attr.attr) + +#define STEP_PRIORITY(step_index, reg_num, priority) \ + tgu_dataset_rw(reg##reg_num, step_index, TGU_PRIORITY##priority, \ + reg_num) + +#define STEP_PRIORITY_LIST(step_index, priority) \ + {STEP_PRIORITY(step_index, 0, priority), \ + STEP_PRIORITY(step_index, 1, priority), \ + STEP_PRIORITY(step_index, 2, priority), \ + STEP_PRIORITY(step_index, 3, priority), \ + STEP_PRIORITY(step_index, 4, priority), \ + STEP_PRIORITY(step_index, 5, priority), \ + STEP_PRIORITY(step_index, 6, priority), \ + STEP_PRIORITY(step_index, 7, priority), \ + STEP_PRIORITY(step_index, 8, priority), \ + STEP_PRIORITY(step_index, 9, priority), \ + STEP_PRIORITY(step_index, 10, priority), \ + STEP_PRIORITY(step_index, 11, priority), \ + STEP_PRIORITY(step_index, 12, priority), \ + STEP_PRIORITY(step_index, 13, priority), \ + STEP_PRIORITY(step_index, 14, priority), \ + STEP_PRIORITY(step_index, 15, priority), \ + STEP_PRIORITY(step_index, 16, priority), \ + STEP_PRIORITY(step_index, 17, priority), \ + NULL \ + } + +#define PRIORITY_ATTRIBUTE_GROUP_INIT(step, priority)\ + (&(const struct attribute_group){\ + .attrs = (struct attribute*[])STEP_PRIORITY_LIST(step, priority),\ + .is_visible = tgu_node_visible,\ + .name = "step" #step "_priority" #priority \ + }) + +enum operation_index { + TGU_PRIORITY0, + TGU_PRIORITY1, + TGU_PRIORITY2, + TGU_PRIORITY3, +}; + +/* Maximum priority that TGU supports */ +#define MAX_PRIORITY 4 + +struct tgu_attribute { + struct device_attribute attr; + u32 step_index; + enum operation_index operation_index; + u32 reg_num; +}; + +struct value_table { + unsigned int *priority; +}; static inline void TGU_LOCK(void __iomem *addr) { @@ -35,6 +143,9 @@ static inline void TGU_UNLOCK(void __iomem *addr) * @dev: Pointer to the associated device structure * @lock: Spinlock for handling concurrent access to private data * @enabled: Flag indicating whether the TGU device is enabled + * @value_table: Store given value based on relevant parameters + * @num_reg: Maximum number of registers + * @num_step: Maximum step size * * This structure defines the data associated with a TGU device, * including its base address, device pointers, clock, spinlock for @@ -46,6 +157,9 @@ struct tgu_drvdata { struct device *dev; spinlock_t lock; bool enabled; + struct value_table *value_table; + int num_reg; + int num_step; }; #endif -- 2.34.1