From: Andre Przywara <andre.przywara@arm.com>
To: Michal Piekos <michal.piekos@mmpsystems.pl>
Cc: Daniel Lezcano <daniel.lezcano@kernel.org>,
Thomas Gleixner <tglx@kernel.org>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Chen-Yu Tsai <wens@kernel.org>,
Jernej Skrabec <jernej.skrabec@gmail.com>,
Samuel Holland <samuel@sholland.org>,
Maxime Ripard <mripard@kernel.org>,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-sunxi@lists.linux.dev
Subject: Re: [PATCH 2/4] clocksource/drivers/sun5i: add H616 hstimer support
Date: Mon, 20 Apr 2026 00:39:15 +0200 [thread overview]
Message-ID: <20260420003915.18c0d5f7@ryzen.lan> (raw)
In-Reply-To: <20260419-h616-t113s-hstimer-v1-2-1af74ebef7c5@mmpsystems.pl>
On Sun, 19 Apr 2026 14:46:08 +0200
Michal Piekos <michal.piekos@mmpsystems.pl> wrote:
Hi,
> H616 high speed timer differs from existing timer-sun5i by register base
> offset.
>
> Add selectable register layout structures.
> Add H616 compatible string to OF match table.
>
> Signed-off-by: Michal Piekos <michal.piekos@mmpsystems.pl>
> ---
> drivers/clocksource/timer-sun5i.c | 56 ++++++++++++++++++++++++++++++++++-----
> 1 file changed, 50 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/clocksource/timer-sun5i.c b/drivers/clocksource/timer-sun5i.c
> index f827d3f98f60..125abc11c3c3 100644
> --- a/drivers/clocksource/timer-sun5i.c
> +++ b/drivers/clocksource/timer-sun5i.c
> @@ -21,18 +21,52 @@
> #define TIMER_IRQ_EN_REG 0x00
> #define TIMER_IRQ_EN(val) BIT(val)
> #define TIMER_IRQ_ST_REG 0x04
> -#define TIMER_CTL_REG(val) (0x20 * (val) + 0x10)
> #define TIMER_CTL_ENABLE BIT(0)
> #define TIMER_CTL_RELOAD BIT(1)
> -#define TIMER_CTL_CLK_PRES(val) (((val) & 0x7) << 4)
> #define TIMER_CTL_ONESHOT BIT(7)
> -#define TIMER_INTVAL_LO_REG(val) (0x20 * (val) + 0x14)
> -#define TIMER_INTVAL_HI_REG(val) (0x20 * (val) + 0x18)
> -#define TIMER_CNTVAL_LO_REG(val) (0x20 * (val) + 0x1c)
> -#define TIMER_CNTVAL_HI_REG(val) (0x20 * (val) + 0x20)
> +#define TIMER_CTL_CLK_PRES(val) (((val) & 0x7) << 4)
> +#define TIMER_CTL_REG(val) \
> + (soc_base->stride * (val) + soc_base->ctl_base)
> +#define TIMER_INTVAL_LO_REG(val) \
> + (soc_base->stride * (val) + soc_base->intval_lo_base)
> +#define TIMER_INTVAL_HI_REG(val) \
> + (soc_base->stride * (val) + soc_base->intval_hi_base)
> +#define TIMER_CNTVAL_LO_REG(val) \
> + (soc_base->stride * (val) + soc_base->cntval_lo_base)
> +#define TIMER_CNTVAL_HI_REG(val) \
> + (soc_base->stride * (val) + soc_base->cntval_hi_base)
>
> #define TIMER_SYNC_TICKS 3
>
> +struct sunxi_timer_base {
> + u32 ctl_base;
> + u32 intval_lo_base;
> + u32 intval_hi_base;
> + u32 cntval_lo_base;
> + u32 cntval_hi_base;
> + u32 stride;
> +};
> +
> +static const struct sunxi_timer_base sun5i_base = {
> + .ctl_base = 0x10,
> + .intval_lo_base = 0x14,
> + .intval_hi_base = 0x18,
> + .cntval_lo_base = 0x1c,
> + .cntval_hi_base = 0x20,
Mmmh, why all these members? Aren't those all the same, just offset by
0x10? So we just need a single value reg_offs, being either 0x0 or 0x10?
> + .stride = 0x20
What it this about? It's the same stride for both versions, so why is
this a field?
> +};
> +
> +static const struct sunxi_timer_base sun50i_base = {
> + .ctl_base = 0x20,
> + .intval_lo_base = 0x24,
> + .intval_hi_base = 0x28,
> + .cntval_lo_base = 0x2c,
> + .cntval_hi_base = 0x30,
> + .stride = 0x20
> +};
> +
> +static const struct sunxi_timer_base *soc_base;
This doesn't look right. Differentiating between slightly different
hardware revision via the compatible string is a common pattern, look
at for instance drivers/media/rc/sunxi-cir.c and its usage of quirks for
an example how to handle this more nicely.
Cheers,
Andre
> +
> struct sun5i_timer {
> void __iomem *base;
> struct clk *clk;
> @@ -238,6 +272,7 @@ static int sun5i_setup_clockevent(struct platform_device *pdev,
> static int sun5i_timer_probe(struct platform_device *pdev)
> {
> struct device *dev = &pdev->dev;
> + struct device_node *node = dev_of_node(&pdev->dev);
> struct sun5i_timer *st;
> struct reset_control *rstc;
> void __iomem *timer_base;
> @@ -251,6 +286,14 @@ static int sun5i_timer_probe(struct platform_device *pdev)
>
> platform_set_drvdata(pdev, st);
>
> + if (!node)
> + return -EINVAL;
> +
> + if (of_device_is_compatible(node, "allwinner,sun50i-h616-hstimer"))
> + soc_base = &sun50i_base;
> + else
> + soc_base = &sun5i_base;
> +
> timer_base = devm_platform_ioremap_resource(pdev, 0);
> if (IS_ERR(timer_base)) {
> dev_err(dev, "Can't map registers\n");
> @@ -314,6 +357,7 @@ static void sun5i_timer_remove(struct platform_device *pdev)
> static const struct of_device_id sun5i_timer_of_match[] = {
> { .compatible = "allwinner,sun5i-a13-hstimer" },
> { .compatible = "allwinner,sun7i-a20-hstimer" },
> + { .compatible = "allwinner,sun50i-h616-hstimer" },
> {},
> };
> MODULE_DEVICE_TABLE(of, sun5i_timer_of_match);
>
next prev parent reply other threads:[~2026-04-19 22:39 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-04-19 12:46 [PATCH 0/4] Add hstimer support for H616 and T113-S3 Michal Piekos
2026-04-19 12:46 ` [PATCH 1/4] dt-bindings: timer: allwinner,sun5i-a13-hstimer: add " Michal Piekos
2026-04-19 21:21 ` Andre Przywara
2026-04-19 12:46 ` [PATCH 2/4] clocksource/drivers/sun5i: add H616 hstimer support Michal Piekos
2026-04-19 22:39 ` Andre Przywara [this message]
2026-04-19 12:46 ` [PATCH 3/4] arm64: dts: allwinner: h616: add hstimer node Michal Piekos
2026-04-19 12:46 ` [PATCH 4/4] arm: dts: allwinner: t113s: " Michal Piekos
2026-04-19 20:55 ` [PATCH 0/4] Add hstimer support for H616 and T113-S3 Andre Przywara
2026-04-20 11:27 ` Michal Piekos
2026-04-20 14:14 ` Andre Przywara
2026-04-21 14:05 ` Michal Piekos
2026-04-22 13:38 ` Andre Przywara
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