From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CD06DF89246 for ; Tue, 21 Apr 2026 10:00:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=NIbItlj+apdxBcprWow4kHiZSpBwOLEGd2TtyIQmhVg=; b=4BLYD1kRY/gEC7rEpPdukkuvvr mbNstPGDuS6NVGrO5SV8Jcvz9srvkUO59lOWqbfhbdMmuq9qmfrNPX7I48e/H2Zq3h7aWtlYaBOp4 c1XYAkiMR9hXnpacG5xjoKGzZTRLIHTujN2UZ6trYJHShkLH1wyrWR104bHJWigd5sX7cnkLq1OLk YLoheuQWoxYhxQ4IB69ysjYP+xppAPZQwI1QSB3SUHuXueKncrsRzeO5a1oxrlKM2qYlwCUYFz62N SDMSHYvlXUqPUAsTCQ/lgzaVC/YcQBf5SegdI/PksJiyc3e/6c1bVO+59WPsyiJDeua3KSY1PPKHD kQw3Ylvg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1wF7uF-00000008O7e-14Cp; Tue, 21 Apr 2026 10:00:35 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1wF7u6-00000008O4S-0gzU for linux-arm-kernel@lists.infradead.org; Tue, 21 Apr 2026 10:00:34 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 905E826A4; Tue, 21 Apr 2026 03:00:19 -0700 (PDT) Received: from localhost.localdomain (unknown [10.57.89.2]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 6116C3FBCB; Tue, 21 Apr 2026 03:00:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1776765625; bh=UIJtDUN+z+zo0DG+oO5YGtZLAL3sXYneRL8KjOt+TZs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Q/H2JgwyFvCG7duKS/myTTbx3z7hmC+SYOLrQyAGJnMR5Zd6grpBLhkolb3NQ3469 +cAr0q7BNjObN6T0Nzy2QibXB/Y5vokfmlQBLwxokpIQthBFIPRgGspmQh8GZZAiP0 /rkzhpNvg52ZY5DnwaV/8HeTjbMWN3H/AZxPN4SA= From: Catalin Marinas To: stable@vger.kernel.org Cc: Will Deacon , linux-arm-kernel@lists.infradead.org Subject: [PATCH 6.18.y 1/6] arm64: tlb: Allow XZR argument to TLBI ops Date: Tue, 21 Apr 2026 11:00:12 +0100 Message-ID: <20260421100018.335793-2-catalin.marinas@arm.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260421100018.335793-1-catalin.marinas@arm.com> References: <20260421100018.335793-1-catalin.marinas@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260421_030026_240434_3B9985F7 X-CRM114-Status: GOOD ( 10.99 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Mark Rutland commit bfd9c931d19aa59fb8371d557774fa169b15db9a upstream. The TLBI instruction accepts XZR as a register argument, and for TLBI operations with a register argument, there is no functional difference between using XZR or another GPR which contains zeroes. Operations without a register argument are encoded as if XZR were used. Allow the __TLBI_1() macro to use XZR when a register argument is all zeroes. Today this only results in a trivial code saving in __do_compat_cache_op()'s workaround for Neoverse-N1 erratum #1542419. In subsequent patches this pattern will be used more generally. There should be no functional change as a result of this patch. Signed-off-by: Mark Rutland Cc: Catalin Marinas Cc: Marc Zyngier Cc: Oliver Upton Cc: Ryan Roberts Cc: Will Deacon Signed-off-by: Will Deacon Signed-off-by: Catalin Marinas --- arch/arm64/include/asm/tlbflush.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h index 18a5dc0c9a54..0ddb344f83b4 100644 --- a/arch/arm64/include/asm/tlbflush.h +++ b/arch/arm64/include/asm/tlbflush.h @@ -38,12 +38,12 @@ : : ) #define __TLBI_1(op, arg) asm (ARM64_ASM_PREAMBLE \ - "tlbi " #op ", %0\n" \ + "tlbi " #op ", %x0\n" \ ALTERNATIVE("nop\n nop", \ - "dsb ish\n tlbi " #op ", %0", \ + "dsb ish\n tlbi " #op ", %x0", \ ARM64_WORKAROUND_REPEAT_TLBI, \ CONFIG_ARM64_WORKAROUND_REPEAT_TLBI) \ - : : "r" (arg)) + : : "rZ" (arg)) #define __TLBI_N(op, arg, n, ...) __TLBI_##n(op, arg)