From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E3F55F89244 for ; Tue, 21 Apr 2026 10:00:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=RW8zzgzxJxDDBfUlz552tR8FdA+HeoAadAkhJHZZZYw=; b=ynVMyMi7pd2FGxaqW4tKHnEJZz bwSrQOz0iEI8UuClP1AfQEEAc+1u8+tjZvLRDsobcqf7hwuJdI7UTy2P5ljQl2s6bpzYTpgnRRGSX +6Ty75+P1OBg+5nw9BDBu+0KDp+4SPXLaGxAHx47MU0Jjh4pJL6M/M+VLKMa/djYa9TfAXujJ3UK2 WGkWfyoQevBrT/BXKTg61XLzjUThn5SjCoW8IsJRMniGhvHa40+LcFNf0OzeteTw+9/KFv7upEAHC xmI8oJna0No5I/OLdB9cyFvxNrbaO6TLElJ74x3F9P37qHiNVWQdvyrKQ+gUB+arkBbSLHLvdfKbl N2R2N7xA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1wF7uJ-00000008O9T-2UKf; Tue, 21 Apr 2026 10:00:39 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1wF7uA-00000008O5X-1rJN for linux-arm-kernel@lists.infradead.org; Tue, 21 Apr 2026 10:00:34 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4FFB03026; Tue, 21 Apr 2026 03:00:24 -0700 (PDT) Received: from localhost.localdomain (unknown [10.57.89.2]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 1F6D73FBCB; Tue, 21 Apr 2026 03:00:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1776765629; bh=hEgI4tAgeBYfJ8zUJ2BOrFQB5zneozX2dkqPPtbXK+s=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=BjBqCrNmC4vX2SxM+2Oh66t72jpSweZ2dPXobXjIjxsB7wl1JupInpU0CAAP7/FS1 rhbqrXPYiyN02ivG7333SCq4m5davo+ex6ZpYMq4yDrG/+QbOcYamuqJ1T7lfS6F96 Rft5EzR2b7YDC5I6o+KC8azIore9/j8OuxR06Dt4= From: Catalin Marinas To: stable@vger.kernel.org Cc: Will Deacon , linux-arm-kernel@lists.infradead.org Subject: [PATCH 6.18.y 5/6] arm64: cputype: Add C1-Pro definitions Date: Tue, 21 Apr 2026 11:00:16 +0100 Message-ID: <20260421100018.335793-6-catalin.marinas@arm.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260421100018.335793-1-catalin.marinas@arm.com> References: <20260421100018.335793-1-catalin.marinas@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260421_030030_519043_1C01ECED X-CRM114-Status: GOOD ( 10.05 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org commit 2c99561016c591f4c3d5ad7d22a61b8726e79735 upstream. Add cputype definitions for C1-Pro. These will be used for errata detection in subsequent patches. These values can be found in "Table A-303: MIDR_EL1 bit descriptions" in issue 07 of the C1-Pro TRM: https://documentation-service.arm.com/static/6930126730f8f55a656570af Acked-by: Mark Rutland Cc: Will Deacon Cc: James Morse Reviewed-by: Will Deacon Signed-off-by: Catalin Marinas --- arch/arm64/include/asm/cputype.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h index 9b00b75acbf2..18f98fb7ee78 100644 --- a/arch/arm64/include/asm/cputype.h +++ b/arch/arm64/include/asm/cputype.h @@ -98,6 +98,7 @@ #define ARM_CPU_PART_CORTEX_A725 0xD87 #define ARM_CPU_PART_CORTEX_A720AE 0xD89 #define ARM_CPU_PART_NEOVERSE_N3 0xD8E +#define ARM_CPU_PART_C1_PRO 0xD8B #define APM_CPU_PART_XGENE 0x000 #define APM_CPU_VAR_POTENZA 0x00 @@ -189,6 +190,7 @@ #define MIDR_CORTEX_A725 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A725) #define MIDR_CORTEX_A720AE MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A720AE) #define MIDR_NEOVERSE_N3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N3) +#define MIDR_C1_PRO MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_C1_PRO) #define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX) #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX) #define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX)