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Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Matthias Brugger , AngeloGioacchino Del Regno , Balsam CHIHI CC: , , , , , , , , Kuanfu Lu Subject: [PATCH 2/2] thermal: mediatek: lvts: Add MT8189 support Date: Mon, 27 Apr 2026 14:48:30 +0800 Message-ID: <20260427065236.1685057-2-kuanfu.lu@mediatek.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20260427065236.1685057-1-kuanfu.lu@mediatek.com> References: <20260427065236.1685057-1-kuanfu.lu@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260426_235329_788448_D3DC0205 X-CRM114-Status: GOOD ( 20.53 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Kuanfu Lu Add LVTS thermal support for MediaTek MT8189 by adding MT8189-specific controller/sensor topology and platform data for the MCU and AP domains. MT8189 differs from previous SoCs in a few aspects, so extend the driver to handle these variations: - Program the hardware thermal shutdown threshold (tshut) using raw units. - Add per-SoC feature flags to skip clock gating and reset control when they are not required, and to enable Stage-3 monitor interrupt setup. - Pass SoC data into lvts_irq_init() and lvts_ctrl_configure() so the initialization can be configured per platform. This enables monitoring of MT8189 CPU clusters and AP domain sensors (SOC/APU/GPU) with the existing LVTS driver. Signed-off-by: Kuanfu Lu --- drivers/thermal/mediatek/lvts_thermal.c | 142 +++++++++++++++++++++--- 1 file changed, 129 insertions(+), 13 deletions(-) diff --git a/drivers/thermal/mediatek/lvts_thermal.c b/drivers/thermal/mediatek/lvts_thermal.c index a9617d5e0077..9dbd9191e3ba 100644 --- a/drivers/thermal/mediatek/lvts_thermal.c +++ b/drivers/thermal/mediatek/lvts_thermal.c @@ -70,6 +70,7 @@ #define LVTS_HW_FILTER 0x0 #define LVTS_TSSEL_CONF 0x13121110 #define LVTS_CALSCALE_CONF 0x300 +#define LVTS_MONINT_CONF_STAGE3 BIT(31) #define LVTS_MONINT_OFFSET_HIGH_INTEN_SENSOR0 BIT(3) #define LVTS_MONINT_OFFSET_HIGH_INTEN_SENSOR1 BIT(8) @@ -159,6 +160,9 @@ struct lvts_data { int temp_offset; int gt_calib_bit_offset; unsigned int def_calibration; + bool clock_gate_no_need; + bool reset_no_need; + bool conf_stage3_need; u16 msr_offset; }; @@ -1044,7 +1048,7 @@ static void lvts_write_config(struct lvts_ctrl *lvts_ctrl, const u32 *cmds, int } } -static int lvts_irq_init(struct lvts_ctrl *lvts_ctrl) +static int lvts_irq_init(struct lvts_ctrl *lvts_ctrl, const struct lvts_data *lvts_data) { /* * LVTS_PROTCTL : Thermal Protection Sensor Selection @@ -1079,7 +1083,11 @@ static int lvts_irq_init(struct lvts_ctrl *lvts_ctrl) * The LVTS_MONINT register layout is the same as the LVTS_MONINTSTS * register, except we set the bits to enable the interrupt. */ - writel(0, LVTS_MONINT(lvts_ctrl->base)); + + if (lvts_data->conf_stage3_need) + writel(LVTS_MONINT_CONF_STAGE3, LVTS_MONINT(lvts_ctrl->base)); + else + writel(0, LVTS_MONINT(lvts_ctrl->base)); return 0; } @@ -1177,7 +1185,8 @@ static int lvts_ctrl_calibrate(struct device *dev, struct lvts_ctrl *lvts_ctrl) return 0; } -static int lvts_ctrl_configure(struct device *dev, struct lvts_ctrl *lvts_ctrl) +static int lvts_ctrl_configure(struct device *dev, struct lvts_ctrl *lvts_ctrl, + const struct lvts_data *lvts_data) { u32 value; @@ -1279,7 +1288,7 @@ static int lvts_ctrl_configure(struct device *dev, struct lvts_ctrl *lvts_ctrl) value = LVTS_FILTER_INTERVAL << 16 | LVTS_SENSOR_INTERVAL; writel(value, LVTS_MONCTL2(lvts_ctrl->base)); - return lvts_irq_init(lvts_ctrl); + return lvts_irq_init(lvts_ctrl, lvts_data); } static int lvts_ctrl_start(struct device *dev, struct lvts_ctrl *lvts_ctrl) @@ -1420,13 +1429,13 @@ static int lvts_domain_init(struct device *dev, struct lvts_domain *lvts_td, return ret; } - ret = lvts_ctrl_calibrate(dev, lvts_ctrl); + ret = lvts_ctrl_calibrate(dev, lvts_ctrl, lvts_data); if (ret) { dev_dbg(dev, "Failed to calibrate controller"); return ret; } - ret = lvts_ctrl_configure(dev, lvts_ctrl); + ret = lvts_ctrl_configure(dev, lvts_ctrl, lvts_data); if (ret) { dev_dbg(dev, "Failed to configure controller"); return ret; @@ -1458,9 +1467,12 @@ static int lvts_probe(struct platform_device *pdev) if (!lvts_data) return -ENODEV; - lvts_td->clk = devm_clk_get_enabled(dev, NULL); - if (IS_ERR(lvts_td->clk)) - return dev_err_probe(dev, PTR_ERR(lvts_td->clk), "Failed to retrieve clock\n"); + if (!lvts_data->clock_gate_no_need) { + lvts_td->clk = devm_clk_get_enabled(dev, NULL); + if (IS_ERR(lvts_td->clk)) + return dev_err_probe(dev, PTR_ERR(lvts_td->clk), + "Failed to retrieve clock\n"); + } res = platform_get_mem_or_io(pdev, 0); if (!res) @@ -1470,10 +1482,12 @@ static int lvts_probe(struct platform_device *pdev) if (IS_ERR(lvts_td->base)) return dev_err_probe(dev, PTR_ERR(lvts_td->base), "Failed to map io resource\n"); - lvts_td->reset = devm_reset_control_get_by_index(dev, 0); - if (IS_ERR(lvts_td->reset)) - return dev_err_probe(dev, PTR_ERR(lvts_td->reset), "Failed to get reset control\n"); - + if (!lvts_data->reset_no_need) { + lvts_td->reset = devm_reset_control_get_by_index(dev, 0); + if (IS_ERR(lvts_td->reset)) + return dev_err_probe(dev, PTR_ERR(lvts_td->reset), + "Failed to get reset control\n"); + } irq = platform_get_irq(pdev, 0); if (irq < 0) return irq; @@ -1742,6 +1756,78 @@ static const struct lvts_ctrl_data mt8188_lvts_ap_data_ctrl[] = { } }; +static const struct lvts_ctrl_data mt8189_lvts_mcu_data_ctrl[] = { + { + .lvts_sensor = { + { .dt_id = MT8189_MCU_LITTLE_CPU1, + .cal_offsets = { 4, 5, 6 } }, + { .dt_id = MT8189_MCU_LITTLE_CPU2, + .cal_offsets = { 8, 9, 10 } }, + { .dt_id = MT8189_MCU_LITTLE_CPU3, + .cal_offsets = { 12, 13, 14 } }, + { .dt_id = MT8189_MCU_LITTLE_CPU4, + .cal_offsets = { 16, 17, 18 } } + }, + VALID_SENSOR_MAP(1, 1, 1, 1), + .offset = 0x0, + }, + { + .lvts_sensor = { + { .dt_id = MT8189_MCU_LITTLE_CPU5, + .cal_offsets = { 24, 25, 26 } }, + { .dt_id = MT8189_MCU_LITTLE_CPU6, + .cal_offsets = { 28, 29, 30 } }, + { .dt_id = MT8189_MCU_LITTLE_CPU7, + .cal_offsets = { 32, 33, 34 } }, + { .dt_id = MT8189_MCU_LITTLE_CPU8, + .cal_offsets = { 36, 37, 38 } } + }, + VALID_SENSOR_MAP(1, 1, 1, 1), + .offset = 0x100, + }, + { + .lvts_sensor = { + { .dt_id = MT8189_MCU_BIG_CPU1, + .cal_offsets = { 44, 45, 46 } }, + { .dt_id = MT8189_MCU_BIG_CPU2, + .cal_offsets = { 48, 49, 50 } }, + { .dt_id = MT8189_MCU_BIG_CPU3, + .cal_offsets = { 52, 53, 54 } }, + { .dt_id = MT8189_MCU_BIG_CPU4, + .cal_offsets = { 56, 57, 58 } } + }, + VALID_SENSOR_MAP(1, 1, 1, 1), + .offset = 0x200, + } +}; + +static const struct lvts_ctrl_data mt8189_lvts_ap_data_ctrl[] = { + { + .lvts_sensor = { + { .dt_id = MT8189_AP_SOC1, + .cal_offsets = { 64, 65, 66 } }, + { .dt_id = MT8189_AP_SOC2, + .cal_offsets = { 68, 69, 70 } }, + { .dt_id = MT8189_AP_SOC3, + .cal_offsets = { 72, 73, 74 } }, + { .dt_id = MT8189_AP_APU, + .cal_offsets = { 76, 77, 78 } } + }, + VALID_SENSOR_MAP(1, 1, 1, 1), + .offset = 0x0, + }, + { + .lvts_sensor = { + { .dt_id = MT8189_AP_GPU1, + .cal_offsets = { 84, 85, 86 } }, + { .dt_id = MT8189_AP_GPU2, + .cal_offsets = { 88, 89, 90 } } + }, + VALID_SENSOR_MAP(1, 1, 0, 0), + .offset = 0x100, + } +}; + static const struct lvts_ctrl_data mt8192_lvts_mcu_data_ctrl[] = { { .lvts_sensor = { @@ -2087,6 +2173,34 @@ static const struct lvts_data mt8188_lvts_ap_data = { .ops = &lvts_platform_ops_mt7988, }; +static const struct lvts_data mt8189_lvts_ap_data = { + .lvts_ctrl = mt8189_lvts_ap_data_ctrl, + .conn_cmd = default_conn_cmds, + .init_cmd = default_init_cmds, + .num_lvts_ctrl = ARRAY_SIZE(mt8189_lvts_ap_data_ctrl), + .num_conn_cmd = ARRAY_SIZE(default_conn_cmds), + .num_init_cmd = ARRAY_SIZE(default_init_cmds), + .temp_factor = LVTS_COEFF_A_MT8195, + .temp_offset = LVTS_COEFF_B_MT8195, + .gt_calib_bit_offset = 0, + .def_calibration = 35000, + .clock_gate_no_need = true, + .reset_no_need = true, + .conf_stage3_need = true, +}; + +static const struct lvts_data mt8189_lvts_mcu_data = { + .lvts_ctrl = mt8189_lvts_mcu_data_ctrl, + .num_lvts_ctrl = ARRAY_SIZE(mt8189_lvts_mcu_data_ctrl), + .temp_factor = LVTS_COEFF_A_MT8195, + .temp_offset = LVTS_COEFF_B_MT8195, + .gt_calib_bit_offset = 0, + .def_calibration = 35000, + .clock_gate_no_need = true, + .reset_no_need = true, + .conf_stage3_need = true, +}; + static const struct lvts_data mt8192_lvts_mcu_data = { .lvts_ctrl = mt8192_lvts_mcu_data_ctrl, .conn_cmd = default_conn_cmds, @@ -2177,6 +2291,8 @@ static const struct of_device_id lvts_of_match[] = { { .compatible = "mediatek,mt8186-lvts", .data = &mt8186_lvts_data }, { .compatible = "mediatek,mt8188-lvts-mcu", .data = &mt8188_lvts_mcu_data }, { .compatible = "mediatek,mt8188-lvts-ap", .data = &mt8188_lvts_ap_data }, + { .compatible = "mediatek,mt8189-lvts-mcu", .data = &mt8189_lvts_mcu_data }, + { .compatible = "mediatek,mt8189-lvts-ap", .data = &mt8189_lvts_ap_data }, { .compatible = "mediatek,mt8192-lvts-mcu", .data = &mt8192_lvts_mcu_data }, { .compatible = "mediatek,mt8192-lvts-ap", .data = &mt8192_lvts_ap_data }, { .compatible = "mediatek,mt8195-lvts-mcu", .data = &mt8195_lvts_mcu_data }, -- 2.45.2