Re: [QUESTION] Is the ARM SMMU v3 implementation designed to always ignore SSID when SSID_VALID == 0?

[Joonwon Kang <joonwonkang@google.com>]

Thanks for your prompt and insightful answer!

> Hi,
> 
> On Tue, Apr 28, 2026 at 07:38:59AM +0000, Joonwon Kang wrote:
> > Hi team,
> > 
> > According to the ARM SMMU v3 spec, I believe that SSID should always be
> > ignored when SSID_VALID == 0 and the current ARM SMMU v3 module
> > implementation in the kernel seems to comply with this without exception.
> > For example, when handling an event from SMMU, the implementation checks
> > SSID_VALID(SSV) first and ignores SSID accordingly. If there is any
> > exception to this rule, I believe it is a bug.
> 
> Indeed

Acknowledged.

> 
> > Is it true for all the current and future cases? In other words, is it
> > **mandatory** that the ARM SMMU v3 implementation ignores SSID when
> > SSID_VALID == 0? or there might be some cases where the implementation
> > needs to refer to SSID even when SSID_VALID == 0?
> > 
> > Asking this question since our HW may not be able to clear SSID when
> > SSID_VALID == 0 and so there might be some garbage value in SSID at some
> > point of time(the HW will have a correct SSID when SSID_VALID == 1,
> > though). If the ARM SMMU v3 implementation is to refer to that garbage
> > value for any reason, the result would be devastating.
> 
> At least according to the architecture, SubstreamID is ignored when SSV=0.
> The SMMU is allowed to propagate the garbage:
> 
>   7.3 Event record
> 
>   * SSV: The SubstreamID validity flag
>     - 0: No SubstreamID was provided with the transaction and the SubstreamID field is UNKNOWN.
> 
> But the driver will ignore it.
> 
> Same for PRI queue but in that case the page request wouldn't have a PASID
> TLP prefix.

Although the PRI request without PASID may cause unpleasant ATC flush with
SSV clear in this case, it does not lead to the implementation referring
to the garbage SSID. Is this understanding correct? And while this case
seems to be handled solely by the ARM SMMU v3 implementation, do you see
if there is additional care required on our device driver for this?

Thanks,
Joonwon Kang