From: Richard Zhu <hongxing.zhu@nxp.com>
To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org,
bhelgaas@google.com, frank.li@nxp.com, l.stach@pengutronix.de,
lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org,
s.hauer@pengutronix.de, kernel@pengutronix.de,
festevam@gmail.com
Cc: linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
devicetree@vger.kernel.org, imx@lists.linux.dev,
linux-kernel@vger.kernel.org, Richard Zhu <hongxing.zhu@nxp.com>,
Frank Li <Frank.Li@nxp.com>
Subject: [PATCH v3 1/3] dt-bindings: PCI: imx6q-pcie: Add intr, aer and pme interrupts
Date: Thu, 30 Apr 2026 13:09:52 +0800 [thread overview]
Message-ID: <20260430050954.3467984-2-hongxing.zhu@nxp.com> (raw)
In-Reply-To: <20260430050954.3467984-1-hongxing.zhu@nxp.com>
Add 'intr', 'aer', and 'pme' interrupt entries to the i.MX6Q PCIe binding
to support PCIe event-based interrupts for general controller events,
Advanced Error Reporting, and Power Management Events respectively.
These interrupts are optional for existing variants (imx6q, imx6sx, imx6qp,
imx7d, imx8mq, imx8mm, imx8mp) to maintain backward compatibility with
existing device trees.
For fsl,imx95-pcie, all 5 interrupts (msi, dma, intr, aer, pme) are
mandatory due to hardware requirements.
This introduces an ABI requirement for fsl,imx95-pcie. The i.MX95 hardware
requires dedicated interrupt lines for AER, PME, and general controller
events due to its redesigned interrupt architecture. i.MX95 cannot
function correctly without explicit interrupt routing for error handling,
power management and link event detection.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
---
.../bindings/pci/fsl,imx6q-pcie.yaml | 30 +++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
index 9d1349855b422..97bbfc5238a20 100644
--- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
@@ -58,12 +58,18 @@ properties:
items:
- description: builtin MSI controller.
- description: builtin DMA controller.
+ - description: PCIe event interrupt.
+ - description: builtin AER SPI standalone interrupt line.
+ - description: builtin PME SPI standalone interrupt line.
interrupt-names:
minItems: 1
items:
- const: msi
- const: dma
+ - const: intr
+ - const: aer
+ - const: pme
reset-gpio:
description: Should specify the GPIO for controlling the PCI bus device
@@ -231,6 +237,30 @@ allOf:
- const: ref
- const: extref # Optional
+ interrupts:
+ minItems: 5
+ interrupt-names:
+ minItems: 5
+
+ - if:
+ properties:
+ compatible:
+ enum:
+ - fsl,imx6q-pcie
+ - fsl,imx6sx-pcie
+ - fsl,imx6qp-pcie
+ - fsl,imx7d-pcie
+ - fsl,imx8mm-pcie
+ - fsl,imx8mp-pcie
+ - fsl,imx8mq-pcie
+ - fsl,imx8q-pcie
+ then:
+ properties:
+ interrupts:
+ maxItems: 2
+ interrupt-names:
+ maxItems: 2
+
unevaluatedProperties: false
examples:
--
2.37.1
next prev parent reply other threads:[~2026-04-30 5:08 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-04-30 5:09 [PATCH v3 0/3] Add root port reset to support link recovery Richard Zhu
2026-04-30 5:09 ` Richard Zhu [this message]
2026-04-30 8:04 ` [PATCH v3 1/3] dt-bindings: PCI: imx6q-pcie: Add intr, aer and pme interrupts Krzysztof Kozlowski
2026-04-30 8:37 ` Hongxing Zhu
2026-04-30 10:48 ` Krzysztof Kozlowski
2026-04-30 5:09 ` [PATCH v3 2/3] arm64: dts: imx95: Add dma, intr, aer and pme interrupters for pcie{0,1} Richard Zhu
2026-04-30 8:04 ` Krzysztof Kozlowski
2026-04-30 8:37 ` Hongxing Zhu
2026-04-30 10:49 ` Krzysztof Kozlowski
2026-04-30 5:09 ` [PATCH v3 3/3] PCI: imx6: Add root port reset to support link recovery Richard Zhu
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