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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: gVjtvZbJHtlggHfNBv+yJ5woHgUxlbNSVTA/PB7PiGBg981a4VaSiCbxhQ9gSboHQIqBHaEZKnssc1nmsDhlEcnT4susauRdV9JOHl+uHqU69VcWxv+RmKlbyQ+qvDUdpWPsh9aLsF8c4NCSKpSDmy93slJ8ksKlxtnuamuilZ3//D3AE8mus7WT9EpqmgaMGcgH7+3DZ7o4kHerp8VikxzQio88lCl+WIJCJ1BkRZymNE5Fha1NOx5y+Ba/2qdGAflLA0/UjHqK7i4g+lwuOSCcHyTR6vV7r5YcL//87ENBRPHthnjOjHxbIi1ZVN1tTfKDZMgGrXa+96VYxWZJrJ/SC1vt2GLoB3ziIYBPtgRI3BKxNLDhR6uGcavQCXG4zN13LlrBzKBsdswdSQ1+v9GPmKBrTw+gP6+gyB+Y5oHTlQHISn+7dkMQtnsJqcdV X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Apr 2026 15:35:41.8822 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 79e0ed34-86cb-4263-3a67-08dea6ce235b X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[4.158.2.129];Helo=[outbound-uk1.az.dlp.m.darktrace.com] X-MS-Exchange-CrossTenant-AuthSource: DU2PEPF00028D05.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: GV2PR08MB9302 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260430_083549_811659_5F76D72B X-CRM114-Status: GOOD ( 19.53 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Formerly the LPI allocaion and freeing was handled by the domains built on top of the LPI domain, and hence the LPI to use was passed in from the child domain. This mandadated that LPI allocation and freeing was done one at a time, rather than for a range of interrupts in one go. Now that the underlying restriction has been removed and all LPI tracking happens within the LPI domain itself, drop the requirement to allocate and free LPIs one-by-one. While we're at it, clean up the IPI allocation to request all LPIs in one go, rather than requesting them one at a time. Incidentally, this fixes a unwind bug for IPIs where previously allocated entries were not unwound on a failed parent allocation. Signed-off-by: Sascha Bischoff --- drivers/irqchip/irq-gic-v5.c | 70 +++++++++++++++++++----------------- 1 file changed, 38 insertions(+), 32 deletions(-) diff --git a/drivers/irqchip/irq-gic-v5.c b/drivers/irqchip/irq-gic-v5.c index a3c9eaa8ff486..61a70fe48bc32 100644 --- a/drivers/irqchip/irq-gic-v5.c +++ b/drivers/irqchip/irq-gic-v5.c @@ -800,17 +800,16 @@ static void gicv5_irq_lpi_domain_free(struct irq_doma= in *domain, unsigned int vi unsigned int nr_irqs) { struct irq_data *d; + int i; =20 - if (WARN_ON_ONCE(nr_irqs !=3D 1)) - return; - - d =3D irq_domain_get_irq_data(domain, virq); - + for (i =3D 0; i < nr_irqs; i++) { + d =3D irq_domain_get_irq_data(domain, virq + i); =20 - release_lpi(d->hwirq); + release_lpi(d->hwirq); =20 - irq_set_handler(virq, NULL); - irq_domain_reset_irq_data(d); + irq_set_handler(virq + i, NULL); + irq_domain_reset_irq_data(d); + } } =20 static int gicv5_irq_lpi_domain_alloc(struct irq_domain *domain, unsigned = int virq, @@ -818,32 +817,38 @@ static int gicv5_irq_lpi_domain_alloc(struct irq_doma= in *domain, unsigned int vi { irq_hw_number_t hwirq; struct irq_data *irqd; - int ret; - - if (WARN_ON_ONCE(nr_irqs !=3D 1)) - return -EINVAL; + int ret, i; =20 - ret =3D alloc_lpi(); - if (ret < 0) - return ret; - hwirq =3D ret; + for (i =3D 0; i < nr_irqs; i++) { + ret =3D alloc_lpi(); + if (ret < 0) + goto out_free_lpis; + hwirq =3D ret; + + ret =3D gicv5_irs_iste_alloc(hwirq); + if (ret < 0) { + /* Undo partial state first, then clean up the rest */ + release_lpi(hwirq); + goto out_free_lpis; + } =20 - irqd =3D irq_domain_get_irq_data(domain, virq); + irqd =3D irq_domain_get_irq_data(domain, virq + i); =20 - irq_domain_set_info(domain, virq, hwirq, &gicv5_lpi_irq_chip, NULL, - handle_fasteoi_irq, NULL, NULL); - irqd_set_single_target(irqd); + irq_domain_set_info(domain, virq + i, hwirq, &gicv5_lpi_irq_chip, + NULL, handle_fasteoi_irq, NULL, NULL); + irqd_set_single_target(irqd); =20 - ret =3D gicv5_irs_iste_alloc(hwirq); - if (ret < 0) { - release_lpi(hwirq); - return ret; + gicv5_hwirq_init(hwirq, GICV5_IRQ_PRI_MI, GICV5_HWIRQ_TYPE_LPI); + gicv5_lpi_config_reset(irqd); } =20 - gicv5_hwirq_init(hwirq, GICV5_IRQ_PRI_MI, GICV5_HWIRQ_TYPE_LPI); - gicv5_lpi_config_reset(irqd); - return 0; + +out_free_lpis: + if (i) + gicv5_irq_lpi_domain_free(domain, virq, i); + + return ret; } =20 static const struct irq_domain_ops gicv5_irq_lpi_domain_ops =3D { @@ -871,11 +876,11 @@ static int gicv5_irq_ipi_domain_alloc(struct irq_doma= in *domain, unsigned int vi struct irq_data *irqd; int ret, i; =20 - for (i =3D 0; i < nr_irqs; i++) { - ret =3D irq_domain_alloc_irqs_parent(domain, virq + i, 1, NULL); - if (ret) - return ret; + ret =3D irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg); + if (ret) + return ret; =20 + for (i =3D 0; i < nr_irqs; i++) { irqd =3D irq_domain_get_irq_data(domain, virq + i); =20 irq_domain_set_hwirq_and_chip(domain, virq + i, i, @@ -903,8 +908,9 @@ static void gicv5_irq_ipi_domain_free(struct irq_domain= *domain, unsigned int vi =20 irq_set_handler(virq + i, NULL); irq_domain_reset_irq_data(d); - irq_domain_free_irqs_parent(domain, virq + i, 1); } + + irq_domain_free_irqs_parent(domain, virq, nr_irqs); } =20 static const struct irq_domain_ops gicv5_irq_ipi_domain_ops =3D { --=20 2.34.1