[PATCH v6 20/25] iommu/arm-smmu-v3-kvm: Share other queues

Mostafa Saleh
2026-05-01T11:20:50Z

Other queues as PRIQ and EVTQ doesn't need to be shadowed. However, we
need to make sure they are in a state that disallow them to be donated
to the hypervisor or guests. So, keep track of those and share them when
they get enabled.

Signed-off-by: Mostafa Saleh <smostafa@google.com>
---
.../iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c | 62 ++++++++++++++++++-
.../iommu/arm/arm-smmu-v3/pkvm/arm_smmu_v3.h | 4 ++
2 files changed, 64 insertions(+), 2 deletions(-)

diff --git a/drivers/iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c
index d92811ef2af5..e258690384f4 100644
--- a/drivers/iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c
+++ b/drivers/iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c
@@ -69,6 +69,16 @@ static bool is_smmu_enabled(struct hyp_arm_smmu_v3_device *smmu)
return FIELD_GET(CR0_SMMUEN, smmu->cr0);
}

+static bool is_evtq_enabled(struct hyp_arm_smmu_v3_device *smmu)
+{
+ return FIELD_GET(CR0_EVTQEN, smmu->cr0);
+}
+
+static bool is_priq_enabled(struct hyp_arm_smmu_v3_device *smmu)
+{
+ return FIELD_GET(CR0_PRIQEN, smmu->cr0);
+}
+
/*
* CMDQ, STE host copies are accessed by the hypervisor, we share them to
* - Prevent the host from passing protected VM memory.
@@ -647,6 +657,14 @@ static void smmu_emulate_cmdq_disable(struct hyp_arm_smmu_v3_device *smmu)
cmdq_size(&smmu->cmdq_host)));
}

+static void smmu_emulate_queue(unsigned long q_base, size_t ent_size_shift)
+{
+ phys_addr_t base = q_base & Q_BASE_ADDR_MASK;
+ size_t size = 1UL << (FIELD_GET(Q_BASE_LOG2SIZE, q_base) + ent_size_shift);
+
+ WARN_ON(smmu_share_pages(base ,size));
+}
+
static bool smmu_dabt_device(struct hyp_arm_smmu_v3_device *smmu,
struct user_pt_regs *regs,
u64 esr, u32 off)
@@ -748,12 +766,31 @@ static bool smmu_dabt_device(struct hyp_arm_smmu_v3_device *smmu,
if (is_write) {
bool last_cmdq_en = is_cmdq_enabled(smmu);
bool last_smmu_en = is_smmu_enabled(smmu);
+ bool last_evtq_en = is_evtq_enabled(smmu);
+ bool last_priq_en = is_priq_enabled(smmu);

smmu->cr0 = val;
if (!last_cmdq_en && is_cmdq_enabled(smmu))
smmu_emulate_cmdq_enable(smmu);
else if (last_cmdq_en && !is_cmdq_enabled(smmu))
smmu_emulate_cmdq_disable(smmu);
+
+ /*
+ * Share PRI and EVTQ to avoid the host using them to write to
+ * protected memory. However, panic on disable for those queues
+ * as that is more complicated, unsharing from here can lead to
+ * use-after-unshare issues, and requires ordering with cr0ack.
+ * As the host never disable those queues, don't support that.
+ */
+ if (!last_evtq_en && is_evtq_enabled(smmu))
+ smmu_emulate_queue(smmu->evtq_base, EVTQ_ENT_SZ_SHIFT);
+ else if (last_evtq_en && !is_evtq_enabled(smmu))
+ WARN_ON(1);
+ if (!last_priq_en && is_priq_enabled(smmu))
+ smmu_emulate_queue(smmu->priq_base, PRIQ_ENT_SZ_SHIFT);
+ else if (last_priq_en && !is_priq_enabled(smmu))
+ WARN_ON(1);
+
if (!last_smmu_en && is_smmu_enabled(smmu))
smmu_emulate_enable(smmu);
else if (last_smmu_en && !is_smmu_enabled(smmu))
@@ -779,6 +816,29 @@ static bool smmu_dabt_device(struct hyp_arm_smmu_v3_device *smmu,
mask = read_write;
break;
}
+ case ARM_SMMU_EVTQ_BASE:
+ if (len != sizeof(u64))
+ break;
+
+ if (is_write) {
+ if (is_evtq_enabled(smmu))
+ break;
+ smmu->evtq_base = val;
+ }
+ mask = read_write;
+ break;
+
+ case ARM_SMMU_PRIQ_BASE:
+ if (len != sizeof(u64))
+ break;
+
+ if (is_write) {
+ if (is_priq_enabled(smmu))
+ break;
+ smmu->priq_base = val;
+ }
+ mask = read_write;
+ break;

/* Allowed 32 bit registers. */
case ARM_SMMU_EVTQ_PROD + SZ_64K:
@@ -801,9 +861,7 @@ static bool smmu_dabt_device(struct hyp_arm_smmu_v3_device *smmu,
mask = read_write;
break;
/* Allowed 64 bit registers. */
- case ARM_SMMU_EVTQ_BASE:
case ARM_SMMU_EVTQ_IRQ_CFG0:
- case ARM_SMMU_PRIQ_BASE:
case ARM_SMMU_PRIQ_IRQ_CFG0:
case ARM_SMMU_GERROR_IRQ_CFG0:
if (len != sizeof(u64))
diff --git a/drivers/iommu/arm/arm-smmu-v3/pkvm/arm_smmu_v3.h b/drivers/iommu/arm/arm-smmu-v3/pkvm/arm_smmu_v3.h
index 6a73cf6b8873..e811d51bdfaa 100644
--- a/drivers/iommu/arm/arm-smmu-v3/pkvm/arm_smmu_v3.h
+++ b/drivers/iommu/arm/arm-smmu-v3/pkvm/arm_smmu_v3.h
@@ -30,6 +30,8 @@
* @host_ste_cfg Host stream table config
* @host_ste_base Host stream table base
* @strtab_cfg Stream table as seen by HW
+ * @evtq_base Host evtq base reg
+ * @priq_base Host priq base reg
*/
struct hyp_arm_smmu_v3_device {
phys_addr_t mmio_addr;
@@ -52,6 +54,8 @@ struct hyp_arm_smmu_v3_device {
u64 host_ste_cfg;
u64 host_ste_base;
struct arm_smmu_strtab_cfg strtab_cfg;
+ unsigned long evtq_base;
+ unsigned long priq_base;
};

extern size_t kvm_nvhe_sym(kvm_hyp_arm_smmu_v3_count);
--
2.54.0.545.g6539524ca2-goog