[PATCH 0/2] PCI: cadence: Add 100 ms delay after link up for speeds > 5 GT/s

[Hans Zhang <18255117159@163.com>]

As per PCIe r6.0, sec 6.6.1, a Downstream Port that supports Link speeds
greater than 5.0 GT/s, software must wait a minimum of 100 ms after Link
training completes before sending a Configuration Request.

The same requirement has already been addressed for the Synopsys
DesignWare PCIe controller in commit 80dc18a0cba8d ("PCI: dwc: Ensure that
dw_pcie_wait_for_link() waits 100 ms after link up").

This series implements the required delay for the Cadence PCIe controller.

Patch 1 introduces a 'max_link_speed' field in struct cdns_pcie and adds
the delay logic in cdns_pcie_host_wait_for_link(). Since max_link_speed
defaults to 0, the delay is not yet triggered. This patch prepares the
infrastructure and references the DWC implementation.

Patch 2 sets the max_link_speed value in the TI J721E glue driver based
on the maximum supported link speed (obtained from the device tree
"max-link-speed" property), thereby activating the delay when the
controller supports speeds greater than 5 GT/s.

Other Cadence-based glue drivers can be updated similarly in follow-up
work.

---
Our company's product is based on the HPA IP from Cadence. When connecting
to different devices, we encountered issues with the enumeration failure
when connecting to the NVIDIA RTX5070 GPU and the NVMe SSD with PCIe 5.0
interface. Our code is based on: 80dc18a0cba8d ("PCI: dwc: Ensure that
dw_pcie_wait_for_link() waits 100 ms after link up").
---

Hans Zhang (2):
  PCI: cadence: Ensure that cdns_pcie_host_wait_for_link() waits 100 ms
    after link up
  PCI: j721e: Set max_link_speed to enable 100 ms delay after link up

 drivers/pci/controller/cadence/pci-j721e.c               | 1 +
 .../pci/controller/cadence/pcie-cadence-host-common.c    | 9 +++++++++
 drivers/pci/controller/cadence/pcie-cadence.h            | 2 ++
 3 files changed, 12 insertions(+)


base-commit: e75a43c7cec459a07d91ed17de4de13ede2b7758
-- 
2.34.1