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(unknown []) by gzga-smtp-mtada-g0-3 (Coremail) with SMTP id _____wCH4HBbyPRpuOd_Cw--.58479S4; Fri, 01 May 2026 23:35:57 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: bhelgaas@google.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, vigneshr@ti.com Cc: robh@kernel.org, s-vadapalli@ti.com, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH 2/2] PCI: j721e: Set max_link_speed to enable 100 ms delay after link up Date: Fri, 1 May 2026 23:35:53 +0800 Message-Id: <20260501153553.66382-3-18255117159@163.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260501153553.66382-1-18255117159@163.com> References: <20260501153553.66382-1-18255117159@163.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CM-TRANSID: _____wCH4HBbyPRpuOd_Cw--.58479S4 X-Coremail-Antispam: 1Uf129KBjvJXoW7uF1xXry8try3ZF17tFy8AFb_yoW8Gr1Dpa y7GFWxG3WIqrW5uanrZ3W5XFyaqFn8J3y7GrZag3WxZFnxCr93JFyIqFyfJ3ySkF4kAF13 A3Zrt342qr43tF7anT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0zZg4U5UUUUU= X-Originating-IP: [240e:b8f:927e:5900:a6da:de99:5aab:66f2] X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/xtbC6x3ghGn0yF2uugAA3O X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260501_163633_424440_95A23801 X-CRM114-Status: UNSURE ( 8.87 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Set cdns_pcie.max_link_speed to the maximum supported link speed (obtained from the device tree property "max-link-speed") in j721e_pcie_set_link_speed(). This activates the post-link delay logic added in cdns_pcie_host_wait_for_link() when the controller supports speeds greater than 5 GT/s. As required by PCIe r6.0 sec 6.6.1, and following the same approach as commit 80dc18a0cba8d ("PCI: dwc: Ensure that dw_pcie_wait_for_link() waits 100 ms after link up"), this ensures a 100 ms delay after link training completes before any Configuration Request is sent. Signed-off-by: Hans Zhang <18255117159@163.com> --- drivers/pci/controller/cadence/pci-j721e.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c index bfdfe98d5aba..ee85b8e04f5b 100644 --- a/drivers/pci/controller/cadence/pci-j721e.c +++ b/drivers/pci/controller/cadence/pci-j721e.c @@ -206,6 +206,7 @@ static int j721e_pcie_set_link_speed(struct j721e_pcie *pcie, (pcie_get_link_speed(link_speed) == PCI_SPEED_UNKNOWN)) link_speed = 2; + pcie->cdns_pcie.max_link_speed = link_speed; val = link_speed - 1; ret = regmap_update_bits(syscon, offset, GENERATION_SEL_MASK, val); if (ret) -- 2.34.1