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Sun, 3 May 2026 06:54:20 -0700 From: Nicolin Chen To: Will Deacon CC: Joerg Roedel , Jean-Philippe Brucker , Robin Murphy , Jason Gunthorpe , Pranjal Shrivastava , Catalin Marinas , =?UTF-8?q?Miko=C5=82aj=20Lenczewski?= , , , Subject: [PATCH] iommu/arm-smmu-v3-sva: Enable Hardware Access and Hardware Dirty bits Date: Sun, 3 May 2026 06:54:12 -0700 Message-ID: <20260503135413.1108138-1-nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001CA:EE_|DM4PR12MB5769:EE_ X-MS-Office365-Filtering-Correlation-Id: 3c3e7171-bafa-4001-01f5-08dea91b7e8e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|82310400026|36860700016|1800799024|56012099003|18002099003; X-Microsoft-Antispam-Message-Info: WJxGblC0gWUr8XzCgqCK4BixBVW8JH74WcDT5p2EIxUJRipM2Qm2z0wpI4IuloiDFqCKRda0w9Gdnl9y8nH5Tf6xAte9S2vOid3bVsBf25x69iKcU64RML0o/4kthOVX8Y2j4+NaLDSWmU8M40jzD8WfXL2pMr+vuLNwN+zNOIlUmcymkuA2/hVHSb11sEym7G295o20qFvnn4DxejVyhvK9FTyAe43k7bLIllKndohralbvJayuVu3NdKQzbZD3bU7tHI/mzxkEYm/CWaJO1ukuah63MPUS4+e1IUh0R674ebE0rUK+ftZJHU7wv+h02oE5AYyOjdRO/ko+xpfaDR8Kq1KcB1w835YRaTx72Owj6VDZFcCiAOi4odgHQB0W4TBsaNOF02Ig16JJ+GP53ai7IgHgdb8K5RNpAh0r+2/LdMxAlUefzrdTsb07VPQea1fQbXnSUw3gSk3wf4IcKp1dXBkC9WMIMevLbHLHbT+DGssk+dlOqQcVJmU8FmJzKlBlNn4WpbFCtgPRx35FugLQvaTfXBpjuPK9h6/52KCWi1WdCxSF7pASum2N54p9XuVdyNC0pNPq9RCGtu4w3BSm1OgNLyoHRN6xB7YUg+Lt/0n9xy/fUbFFeVvZZkcj5F176TU6HHuoIApa350nEBiUrqLvK0kP+JfNKcS1UqhzTbTTWpoPzVqX3SWLvHj4kx8DMC92xk+gOqsr1kBwWFXUlbZehWHkUt+rN6mlMXo= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(7416014)(82310400026)(36860700016)(1800799024)(56012099003)(18002099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: F/WLmtxD6MMFSbzwMFAIFVr9NxTQsXUzLqUFb6crZglcG89UOTrMO6g+4Bkr94yBDn4aN/oSTVR8LpFoQoxPlNJ/51v0itxtKs13KPHlbFpy6UhHEcZw+SvewFz9gpmsN6cVtyB34ZVeBH9oFJyd3uq/r+rt0MMUzHDRkQehSbk5RQBoqy0BfFFWBgevPwfFSzwRgzwm/Pcj9gDUqn7lH7JocQJ8XQdTV9m6ugwpbAW1QwpwUTT8rLet0x/hM0H8nyxolWhcxZhM+c+9kSM8+CgfBPLxIxJ5W1VQeaDHSq5RjnBPNQ6fx5yDyLCZpddclNE/hZtoYZim/Wpj/abBZf/CY/Yw+rNXVwdy1DLRazMSJq4BLIIpDztWYkFC51tbhoFAI19iNg7EIftXqv9wFYUPbetNBQyHq8i8zo4gwOzL93N86Fpu6Cv0nNJU8OYa X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 May 2026 13:54:28.5037 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3c3e7171-bafa-4001-01f5-08dea91b7e8e X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001CA.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5769 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260503_065437_057763_C7E1F7AB X-CRM114-Status: GOOD ( 11.11 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org HTTU is introduced by utilizing the Dirty Bit Modifier (DBM) in the PTE. When kernel maps a clean but writable page, it will set PTE_READONLY and PTE_DBM (aka PTE_WRITE) at the same time. When a write occurs, an HTTU- capable MMU will automatically clear the PTE_RDONLY bit without software intervention. On the other hand, SMMU has the same HTTU feature, yet it is not enabled in the SVA CD. As a result, SMMU will not clear the PTE_RDONLY bit while sharing the CPU page table, resulting in unnecessary stalls. Thus, enable CTXDESC_CD_0_TCR_HA and CTXDESC_CD_0_TCR_HD in the SVA CD. Suggested-by: Jason Gunthorpe Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c index f1f8e01a7e914..1ed8a6f29dc44 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c @@ -92,6 +92,16 @@ void arm_smmu_make_sva_cd(struct arm_smmu_cd *target, target->data[1] = cpu_to_le64(virt_to_phys(mm->pgd) & CTXDESC_CD_1_TTB0_MASK); + + /* + * Enable Hardware Access and Dirty updates (DBM) if supported. + * This is safe to enable by default, as PTE_WRITE and PTE_DBM + * share the same bit. + */ + if (master->smmu->features & ARM_SMMU_FEAT_HA) + target->data[0] |= cpu_to_le64(CTXDESC_CD_0_TCR_HA); + if (master->smmu->features & ARM_SMMU_FEAT_HD) + target->data[0] |= cpu_to_le64(CTXDESC_CD_0_TCR_HD); } else { target->data[0] |= cpu_to_le64(CTXDESC_CD_0_TCR_EPD0); -- 2.43.0