[PATCH 7/8] arm64: dts: qcom: lemans: add AEST error nodes

Umang Chheda
2026-05-05T12:25:46Z

Add AEST RAS error source nodes for the Lemans SoC.

The DT describes a processor error source covering all CPU cores and a
shared L3 cache error source for the cluster. These nodes model the
hardware error reporting blocks and associated interrupts as required
by the Arm AEST specification.

Co-developed-by: Faruque Ansari <faruque.ansari@oss.qualcomm.com>
Signed-off-by: Faruque Ansari <faruque.ansari@oss.qualcomm.com>
Signed-off-by: Umang Chheda <umang.chheda@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/lemans.dtsi | 41 ++++++++++++++++++++++++++++++++++++
1 file changed, 41 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi
index fe6e76351823..199ea1f9a8d5 100644
--- a/arch/arm64/boot/dts/qcom/lemans.dtsi
+++ b/arch/arm64/boot/dts/qcom/lemans.dtsi
@@ -4,6 +4,7 @@
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/

+#include <dt-bindings/arm/aest.h>
#include <dt-bindings/interconnect/qcom,icc.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
@@ -29,6 +30,46 @@ / {
#address-cells = <2>;
#size-cells = <2>;

+ aest {
+ compatible = "arm,aest";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ aest-processor-0 {
+ compatible = "arm,aest-processor";
+ arm,num-records = <1>;
+ arm,record-impl = /bits/ 64 <0x0>;
+ arm,status-reporting = /bits/ 64 <0x0>;
+ arm,addressing-mode = /bits/ 64 <0x0>;
+ arm,processor-flags = <AEST_PROC_GLOBAL>;
+ interrupts = <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-names = "fhi";
+ };
+
+ aest-l3-cluster0 {
+ compatible = "arm,aest-processor";
+ arm,num-records = <2>;
+ arm,record-impl = /bits/ 64 <0x1>;
+ arm,status-reporting = /bits/ 64 <0x0>;
+ arm,addressing-mode = /bits/ 64 <0x0>;
+ arm,processor-flags = <AEST_PROC_SHARED>;
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "fhi";
+ };
+
+ aest-l3-cluster1 {
+ compatible = "arm,aest-processor";
+ arm,num-records = <2>;
+ arm,record-impl = /bits/ 64 <0x1>;
+ arm,status-reporting = /bits/ 64 <0x0>;
+ arm,addressing-mode = /bits/ 64 <0x0>;
+ arm,processor-flags = <AEST_PROC_SHARED>;
+ interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "fhi";
+ };
+ };
+
clocks {
xo_board_clk: xo-board-clk {
compatible = "fixed-clock";

--
2.34.1