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X-CSE-ConnectionGUID: 0D5vLf71RqyBSSpqVg3r5g== X-CSE-MsgGUID: Uh3vINQKS9Gh97g3+Vzllw== X-IronPort-AV: E=Sophos;i="6.23,217,1770620400"; d="scan'208";a="56268042" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 May 2026 00:14:09 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.87.152) by chn-vm-ex4.mchp-main.com (10.10.87.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.2.2562.37; Tue, 5 May 2026 00:14:08 -0700 Received: from che-lt-i67131.microchip.com (10.10.85.11) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Tue, 5 May 2026 00:14:00 -0700 From: Manikandan Muralidharan To: , , , , , , , , , , , , , , , , , , , , , , CC: Subject: [PATCH v5 3/5] i3c: mipi-i3c-hci: add microchip sama7d65 SoC compatible with the required quirk Date: Tue, 5 May 2026 12:43:25 +0530 Message-ID: <20260505071327.125787-4-manikandan.m@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20260505071327.125787-1-manikandan.m@microchip.com> References: <20260505071327.125787-1-manikandan.m@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260505_001410_188648_335172EA X-CRM114-Status: GOOD ( 14.63 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add support for microchip sama7d65 SoC I3C HCI master only IP with additional clock support to enable bulk clock acquisition Signed-off-by: Manikandan Muralidharan --- Changes in v5: - Remove HCI_QUIRK_CLK_SUPPORT quirk and call devm_clk_bulk_get_all_enabled unconditionally Changes in v4: - Remove the clock index variable MCHP_I3C_CLK_IDX Changes in v3: - Make use of existing HCI_QUIRK_* code base - Introduce HCI_QUIRK_CLK_SUPPORT to handle/enable the required Peripheral and system generic clk in bulk Changes in v2: - Platform specific changes are integrated in the existing mipi-i3c-hci driver by introducing separate MCHP_HCI_QUIRK_* quirks and vendor specific quirk files --- drivers/i3c/master/mipi-i3c-hci/core.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/i3c/master/mipi-i3c-hci/core.c b/drivers/i3c/master/mipi-i3c-hci/core.c index b781dbed2165..20d32a9eb62c 100644 --- a/drivers/i3c/master/mipi-i3c-hci/core.c +++ b/drivers/i3c/master/mipi-i3c-hci/core.c @@ -8,6 +8,7 @@ */ #include +#include #include #include #include @@ -970,6 +971,7 @@ static int i3c_hci_probe(struct platform_device *pdev) { const struct mipi_i3c_hci_platform_data *pdata = pdev->dev.platform_data; struct i3c_hci *hci; + struct clk_bulk_data *clks; int irq, ret; hci = devm_kzalloc(&pdev->dev, sizeof(*hci), GFP_KERNEL); @@ -1001,6 +1003,11 @@ static int i3c_hci_probe(struct platform_device *pdev) if (!hci->quirks && platform_get_device_id(pdev)) hci->quirks = platform_get_device_id(pdev)->driver_data; + ret = devm_clk_bulk_get_all_enabled(&pdev->dev, &clks); + if (ret < 0) + return dev_err_probe(&pdev->dev, ret, + "Failed to get clocks\n"); + ret = i3c_hci_init(hci); if (ret) return ret; @@ -1031,6 +1038,9 @@ static void i3c_hci_remove(struct platform_device *pdev) static const __maybe_unused struct of_device_id i3c_hci_of_match[] = { { .compatible = "mipi-i3c-hci", }, + { .compatible = "microchip,sama7d65-i3c-hci", + .data = (void *)(HCI_QUIRK_PIO_MODE | HCI_QUIRK_OD_PP_TIMING | + HCI_QUIRK_RESP_BUF_THLD) }, {}, }; MODULE_DEVICE_TABLE(of, i3c_hci_of_match); -- 2.25.1