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(unknown []) by gzga-smtp-mtada-g0-0 (Coremail) with SMTP id _____wCHAqsXXftpv5CgDg--.43926S4; Wed, 06 May 2026 23:24:11 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: bhelgaas@google.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, vigneshr@ti.com, jingoohan1@gmail.com, thomas.petazzoni@bootlin.com, pali@kernel.org, ryder.lee@mediatek.com, jianjun.wang@mediatek.com, claudiu.beznea.uj@bp.renesas.com, mpillai@cadence.com Cc: robh@kernel.org, s-vadapalli@ti.com, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-renesas-soc@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH v2 2/8] PCI: cadence: LGA: Add max_link_speed field and 100 ms delay after link training Date: Wed, 6 May 2026 23:23:40 +0800 Message-Id: <20260506152346.166056-3-18255117159@163.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260506152346.166056-1-18255117159@163.com> References: <20260506152346.166056-1-18255117159@163.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CM-TRANSID: _____wCHAqsXXftpv5CgDg--.43926S4 X-Coremail-Antispam: 1Uf129KBjvJXoW7ZFWfZryUWw43Wr43uw17ZFb_yoW5JFWfpa yDWryfGF1IqrWY9a1kZa4UXryaq3Z8C347tws2k34xWr17CrW5JF42gF1fJFy3KrZrZry7 ZF1DtF9rGr4ayFUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0ziM7KxUUUUU= X-Originating-IP: [240e:b8f:927e:5900:dbee:26f0:1b68:48a4] X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/xtbCxBu2Wmn7XRs43gAA3B X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260506_082450_549781_F38B0510 X-CRM114-Status: GOOD ( 11.88 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The Cadence LGA (Legacy Architecture IP) PCIe host controller currently lacks the mandatory 100 ms delay after link training completes for speeds > 5.0 GT/s, as required by PCIe r6.0 sec 6.6.1. Add a 'max_link_speed' field to struct cdns_pcie to record the maximum supported link speed (or the currently configured speed). In the common host layer function cdns_pcie_host_start_link(), after the link has been successfully established, call pcie_wait_after_link_train() to insert the required delay if max_link_speed > 2. Glue drivers must set max_link_speed appropriately (e.g., from the device tree property "max-link-speed") to enable the delay. Signed-off-by: Hans Zhang <18255117159@163.com> --- drivers/pci/controller/cadence/pcie-cadence-host-common.c | 4 ++++ drivers/pci/controller/cadence/pcie-cadence.h | 2 ++ 2 files changed, 6 insertions(+) diff --git a/drivers/pci/controller/cadence/pcie-cadence-host-common.c b/drivers/pci/controller/cadence/pcie-cadence-host-common.c index 2b0211870f02..51376f69d007 100644 --- a/drivers/pci/controller/cadence/pcie-cadence-host-common.c +++ b/drivers/pci/controller/cadence/pcie-cadence-host-common.c @@ -14,6 +14,7 @@ #include "pcie-cadence.h" #include "pcie-cadence-host-common.h" +#include "../../pci.h" #define LINK_RETRAIN_TIMEOUT HZ @@ -115,6 +116,9 @@ int cdns_pcie_host_start_link(struct cdns_pcie_rc *rc, if (!ret && rc->quirk_retrain_flag) ret = cdns_pcie_retrain(pcie, pcie_link_up); + if (!ret) + pcie_wait_after_link_train(pcie->max_link_speed); + return ret; } EXPORT_SYMBOL_GPL(cdns_pcie_host_start_link); diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h index 574e9cf4d003..e222b095d2b6 100644 --- a/drivers/pci/controller/cadence/pcie-cadence.h +++ b/drivers/pci/controller/cadence/pcie-cadence.h @@ -86,6 +86,7 @@ struct cdns_plat_pcie_of_data { * @ops: Platform-specific ops to control various inputs from Cadence PCIe * wrapper * @cdns_pcie_reg_offsets: Register bank offsets for different SoC + * @max_link_speed: maximum supported link speed */ struct cdns_pcie { void __iomem *reg_base; @@ -98,6 +99,7 @@ struct cdns_pcie { struct device_link **link; const struct cdns_pcie_ops *ops; const struct cdns_plat_pcie_of_data *cdns_pcie_reg_offsets; + int max_link_speed; }; /** -- 2.34.1