[PATCH v1 3/3] clk: clocking-wizard: remove 20kHz restriction

[Colin Foster <colin.foster@in-advantage.com>]

There is a 20KHz minimum target for clock difference that was baked into
the driver. This is unnecessary, and causes target clock frequencies to
be rejected that should otherwise succeed.

The discrepancy existed in versal drivers as well, but was removed as
part of 'commit e0a94c6bb5b4 ("clk: xilinx: Optimize divisor search in
clk_wzrd_get_divisors_ver()")'

Apply the change to allow differences >= 20kHz.

Before the change:

8<--------
clk-wizard-test: requesting 133312000 Hz on output 0 (clock NOT enabled)
*** Clock wizard - Matching for rate 133312000 parent rate 99999000
m = 33, d = 1, o = 25, freq = 131998680, diff = 1313320
m = 35, d = 1, o = 26, freq = 134614038, diff = 1302038
m = 36, d = 1, o = 27, freq = 133332000, diff = 20000
*** Clock wizard - Matching for rate 133312000 parent rate 99999000
m = 33, d = 1, o = 25, freq = 131998680, diff = 1313320
m = 35, d = 1, o = 26, freq = 134614038, diff = 1302038
m = 36, d = 1, o = 27, freq = 133332000, diff = 20000
clk-wizard-test: clk_set_rate(133312000) failed: -22
8<--------

After the change:

8<--------
clk-wizard-test: requesting 133312000 Hz on output 0 (clock NOT enabled)
*** Clock wizard - Matching for rate 133312000 parent rate 99999000
m = 33, d = 1, o = 25, freq = 131998680, diff = 1313320
m = 35, d = 1, o = 26, freq = 134614038, diff = 1302038
m = 36, d = 1, o = 27, freq = 133332000, diff = 20000
*** Clock wizard - Matching for rate 133312000 parent rate 99999000
m = 33, d = 1, o = 25, freq = 131998680, diff = 1313320
m = 35, d = 1, o = 26, freq = 134614038, diff = 1302038
m = 36, d = 1, o = 27, freq = 133332000, diff = 20000
*** Clock wizard - Matching for rate 133332000 parent rate 99999000
m = 33, d = 1, o = 25, freq = 131998680, diff = 1333320
m = 35, d = 1, o = 26, freq = 134614038, diff = 1282038
m = 36, d = 1, o = 27, freq = 133332000, diff = 0
clk-wizard-test: success -- actual rate: 133332000 Hz (requested 133312000 Hz, error 20000 Hz)
8<--------

Signed-off-by: Colin Foster <colin.foster@in-advantage.com>
---
 drivers/clk/xilinx/clk-xlnx-clock-wizard.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/clk/xilinx/clk-xlnx-clock-wizard.c b/drivers/clk/xilinx/clk-xlnx-clock-wizard.c
index d43f20e9ac59..bc71d6155b06 100644
--- a/drivers/clk/xilinx/clk-xlnx-clock-wizard.c
+++ b/drivers/clk/xilinx/clk-xlnx-clock-wizard.c
@@ -105,7 +105,6 @@
 #define VER_WZRD_VCO_MAX		4320000000ULL
 #define VER_WZRD_O_MIN			2
 #define VER_WZRD_O_MAX			511
-#define WZRD_MIN_ERR			20000
 #define WZRD_FRAC_POINTS		1000
 
 /* Get the mask from width */
@@ -425,7 +424,7 @@ static int clk_wzrd_get_divisors(struct clk_hw *hw, unsigned long rate,
 			}
 		}
 	}
-	return best_diff < WZRD_MIN_ERR ? 0 : -EBUSY;
+	return best_diff != -1ULL ? 0 : -EBUSY;
 }
 
 static int clk_wzrd_reconfig(struct clk_wzrd_divider *divider, void __iomem *div_addr)
-- 
2.43.0