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X-CSE-ConnectionGUID: fLd/3yl7QJG0Akpq1sa2Kw== X-CSE-MsgGUID: aZr4Z5IkSvWO+pCroOj05Q== X-IronPort-AV: E=Sophos;i="6.23,221,1770620400"; d="scan'208";a="57163815" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 07 May 2026 01:48:49 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.58; Thu, 7 May 2026 01:48:48 -0700 Received: from che-lt-i67131.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Thu, 7 May 2026 01:48:39 -0700 From: Manikandan Muralidharan To: , , , , , , , , , , , , , , , , , , , , , , , CC: Subject: [PATCH v6 3/5] i3c: mipi-i3c-hci: add microchip sama7d65 SoC compatible with the required quirk Date: Thu, 7 May 2026 14:18:03 +0530 Message-ID: <20260507084805.481737-4-manikandan.m@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20260507084805.481737-1-manikandan.m@microchip.com> References: <20260507084805.481737-1-manikandan.m@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260507_014849_843379_4218BD38 X-CRM114-Status: GOOD ( 15.60 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add support for microchip sama7d65 SoC I3C HCI master only IP with additional clock support to enable bulk clock acquisition Reviewed-by: Adrian Hunter Signed-off-by: Manikandan Muralidharan --- Changes in v6: - Reorder local variable definitions in i3c_hci_probe in descending order of line length Changes in v5: - Remove HCI_QUIRK_CLK_SUPPORT quirk and call devm_clk_bulk_get_all_enabled unconditionally Changes in v4: - Remove the clock index variable MCHP_I3C_CLK_IDX Changes in v3: - Make use of existing HCI_QUIRK_* code base - Introduce HCI_QUIRK_CLK_SUPPORT to handle/enable the required Peripheral and system generic clk in bulk Changes in v2: - Platform specific changes are integrated in the existing mipi-i3c-hci driver by introducing separate MCHP_HCI_QUIRK_* quirks and vendor specific quirk files drivers/i3c/master/mipi-i3c-hci/core.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/i3c/master/mipi-i3c-hci/core.c b/drivers/i3c/master/mipi-i3c-hci/core.c index b781dbed2165..093a85eedfcb 100644 --- a/drivers/i3c/master/mipi-i3c-hci/core.c +++ b/drivers/i3c/master/mipi-i3c-hci/core.c @@ -8,6 +8,7 @@ */ #include +#include #include #include #include @@ -969,6 +970,7 @@ static int i3c_hci_init(struct i3c_hci *hci) static int i3c_hci_probe(struct platform_device *pdev) { const struct mipi_i3c_hci_platform_data *pdata = pdev->dev.platform_data; + struct clk_bulk_data *clks; struct i3c_hci *hci; int irq, ret; @@ -1001,6 +1003,11 @@ static int i3c_hci_probe(struct platform_device *pdev) if (!hci->quirks && platform_get_device_id(pdev)) hci->quirks = platform_get_device_id(pdev)->driver_data; + ret = devm_clk_bulk_get_all_enabled(&pdev->dev, &clks); + if (ret < 0) + return dev_err_probe(&pdev->dev, ret, + "Failed to get clocks\n"); + ret = i3c_hci_init(hci); if (ret) return ret; @@ -1031,6 +1038,9 @@ static void i3c_hci_remove(struct platform_device *pdev) static const __maybe_unused struct of_device_id i3c_hci_of_match[] = { { .compatible = "mipi-i3c-hci", }, + { .compatible = "microchip,sama7d65-i3c-hci", + .data = (void *)(HCI_QUIRK_PIO_MODE | HCI_QUIRK_OD_PP_TIMING | + HCI_QUIRK_RESP_BUF_THLD) }, {}, }; MODULE_DEVICE_TABLE(of, i3c_hci_of_match); -- 2.25.1