From: Xianwei Zhao via B4 Relay <devnull+xianwei.zhao.amlogic.com@kernel.org>
To: Thomas Gleixner <tglx@kernel.org>,
Neil Armstrong <neil.armstrong@linaro.org>,
Kevin Hilman <khilman@baylibre.com>,
Jerome Brunet <jbrunet@baylibre.com>,
Martin Blumenstingl <martin.blumenstingl@googlemail.com>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Heiner Kallweit <hkallweit1@gmail.com>
Cc: linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-amlogic@lists.infradead.org, devicetree@vger.kernel.org,
Xianwei Zhao <xianwei.zhao@amlogic.com>
Subject: [PATCH 1/3] irqchip/meson-gpio: fix incorrect register address
Date: Fri, 08 May 2026 07:36:54 +0000 [thread overview]
Message-ID: <20260508-a9-gpio-irqchip-v1-1-9dc5f3e022e0@amlogic.com> (raw)
In-Reply-To: <20260508-a9-gpio-irqchip-v1-0-9dc5f3e022e0@amlogic.com>
From: Xianwei Zhao <xianwei.zhao@amlogic.com>
When set gpio irq type(level and single-edge) for S4, register address is
REG_EDGE_POL, not both-edge trigger register. This patch fix it.
Fixes: bbd6fcc76b39 ("irqchip: Add support for Amlogic A4 and A5 SoCs")
Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
---
drivers/irqchip/irq-meson-gpio.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/irqchip/irq-meson-gpio.c b/drivers/irqchip/irq-meson-gpio.c
index f722e9c57e2e..74a376ef452e 100644
--- a/drivers/irqchip/irq-meson-gpio.c
+++ b/drivers/irqchip/irq-meson-gpio.c
@@ -415,8 +415,7 @@ static int meson_s4_gpio_irq_set_type(struct meson_gpio_irq_controller *ctl,
if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
val |= BIT(ctl->params->edge_single_offset + idx);
- meson_gpio_irq_update_bits(ctl, params->edge_pol_reg,
- BIT(idx) | BIT(12 + idx), val);
+ meson_gpio_irq_update_bits(ctl, REG_EDGE_POL, BIT(idx) | BIT(12 + idx), val);
return 0;
};
--
2.52.0
next prev parent reply other threads:[~2026-05-08 7:37 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-08 7:36 [PATCH 0/3] irqchip: Add GPIO interrupt support for Amlogic A9 Xianwei Zhao via B4 Relay
2026-05-08 7:36 ` Xianwei Zhao via B4 Relay [this message]
2026-05-08 7:36 ` [PATCH 2/3] dt-bindings: interrupt-controller: Add support for Amlogic A9 SoCs Xianwei Zhao via B4 Relay
2026-05-08 15:03 ` Conor Dooley
2026-05-08 7:36 ` [PATCH 3/3] irqchip/meson-gpio: " Xianwei Zhao via B4 Relay
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