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Fri, 8 May 2026 19:16:42 +0800 Received: from RTKEXHMBS01.realtek.com.tw (172.21.6.40) by RTKEXHMBS04.realtek.com.tw (10.21.1.54) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Fri, 8 May 2026 19:16:42 +0800 Received: from RTKEXHMBS06.realtek.com.tw (10.21.1.56) by RTKEXHMBS01.realtek.com.tw (172.21.6.40) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.17; Fri, 8 May 2026 19:16:42 +0800 Received: from cn1dhc-k02 (172.21.252.101) by RTKEXHMBS06.realtek.com.tw (10.21.1.56) with Microsoft SMTP Server id 15.2.2562.17 via Frontend Transport; Fri, 8 May 2026 19:16:42 +0800 From: Yu-Chun Lin To: , , , , , , , , CC: , , , , , , , , , Subject: [PATCH v7 03/10] clk: realtek: Introduce a common probe() Date: Fri, 8 May 2026 19:16:34 +0800 Message-ID: <20260508111641.3192177-4-eleanor.lin@realtek.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20260508111641.3192177-1-eleanor.lin@realtek.com> References: <20260508111641.3192177-1-eleanor.lin@realtek.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260508_121751_266895_E828A5D6 X-CRM114-Status: GOOD ( 22.08 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Cheng-Yu Lee Add rtk_clk_probe() to set up the shared regmap, register clock hardware, and add the clock provider. Additionally, if the "#reset-cells" property is present in the device tree, it creates and registers an auxiliary device using the provided aux_name. This allows the dedicated reset driver to bind to this device, enabling both clock and reset drivers to share the same regmap. Signed-off-by: Cheng-Yu Lee Co-developed-by: Yu-Chun Lin Signed-off-by: Yu-Chun Lin --- MAINTAINERS | 1 + drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 1 + drivers/clk/realtek/Kconfig | 28 +++++++++++++++ drivers/clk/realtek/Makefile | 4 +++ drivers/clk/realtek/common.c | 66 ++++++++++++++++++++++++++++++++++++ drivers/clk/realtek/common.h | 37 ++++++++++++++++++++ 7 files changed, 138 insertions(+) create mode 100644 drivers/clk/realtek/Kconfig create mode 100644 drivers/clk/realtek/Makefile create mode 100644 drivers/clk/realtek/common.c create mode 100644 drivers/clk/realtek/common.h diff --git a/MAINTAINERS b/MAINTAINERS index ff0347f6556d..b16d2c62ea3d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -22434,6 +22434,7 @@ L: devicetree@vger.kernel.org L: linux-clk@vger.kernel.org S: Supported F: Documentation/devicetree/bindings/clock/realtek* +F: drivers/clk/realtek/* F: drivers/reset/realtek/* F: include/dt-bindings/clock/realtek* F: include/dt-bindings/reset/realtek* diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index b2efbe9f6acb..8bf262dd23a9 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -519,6 +519,7 @@ source "drivers/clk/nuvoton/Kconfig" source "drivers/clk/pistachio/Kconfig" source "drivers/clk/qcom/Kconfig" source "drivers/clk/ralink/Kconfig" +source "drivers/clk/realtek/Kconfig" source "drivers/clk/renesas/Kconfig" source "drivers/clk/rockchip/Kconfig" source "drivers/clk/samsung/Kconfig" diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index a3e2862ebd7e..e226bee2d039 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -140,6 +140,7 @@ obj-$(CONFIG_COMMON_CLK_PISTACHIO) += pistachio/ obj-$(CONFIG_COMMON_CLK_PXA) += pxa/ obj-$(CONFIG_COMMON_CLK_QCOM) += qcom/ obj-y += ralink/ +obj-$(CONFIG_COMMON_CLK_REALTEK) += realtek/ obj-y += renesas/ obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/ obj-$(CONFIG_COMMON_CLK_SAMSUNG) += samsung/ diff --git a/drivers/clk/realtek/Kconfig b/drivers/clk/realtek/Kconfig new file mode 100644 index 000000000000..4e042e41f30d --- /dev/null +++ b/drivers/clk/realtek/Kconfig @@ -0,0 +1,28 @@ +# SPDX-License-Identifier: GPL-2.0-only +config COMMON_CLK_REALTEK + tristate "Clock driver for Realtek SoCs" + depends on ARCH_REALTEK || COMPILE_TEST + default ARCH_REALTEK + help + Enable the common clock framework infrastructure for Realtek + system-on-chip platforms. + + This provides the base support required by individual Realtek + clock controller drivers to expose clocks to peripheral devices. + + If you have a Realtek-based platform, say Y. + +if COMMON_CLK_REALTEK + +config RTK_CLK_COMMON + tristate "Realtek Clock Common" + select RESET_RTK_COMMON + select AUXILIARY_BUS + help + Common helper code shared by Realtek clock controller drivers. + + This provides utility functions and data structures used by + multiple Realtek clock implementations, and include integration + with reset controllers where required. + +endif diff --git a/drivers/clk/realtek/Makefile b/drivers/clk/realtek/Makefile new file mode 100644 index 000000000000..377ec776ee47 --- /dev/null +++ b/drivers/clk/realtek/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only +obj-$(CONFIG_RTK_CLK_COMMON) += clk-rtk.o + +clk-rtk-y += common.o diff --git a/drivers/clk/realtek/common.c b/drivers/clk/realtek/common.c new file mode 100644 index 000000000000..56f6ba1af6ef --- /dev/null +++ b/drivers/clk/realtek/common.c @@ -0,0 +1,66 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2019-2026 Realtek Semiconductor Corporation + * Author: Cheng-Yu Lee + */ + +#include +#include +#include +#include +#include +#include +#include "common.h" + +static int rtk_reset_controller_register(struct device *dev, const char *aux_name, + struct regmap *map) +{ + struct auxiliary_device *adev; + + if (!of_property_present(dev->of_node, "#reset-cells")) + return 0; + + adev = devm_auxiliary_device_create(dev, aux_name, (void *)map); + + if (IS_ERR(adev)) + return PTR_ERR(adev); + + return 0; +} + +int rtk_clk_probe(struct platform_device *pdev, const struct rtk_clk_desc *desc, + const char *aux_name) +{ + struct device *dev = &pdev->dev; + struct regmap *regmap; + int i, ret; + + regmap = device_node_to_regmap(dev->of_node); + if (IS_ERR(regmap)) + return dev_err_probe(dev, PTR_ERR(regmap), "failed to get regmap\n"); + + for (i = 0; i < desc->num_clks; i++) + desc->clks[i]->regmap = regmap; + + for (i = 0; i < desc->clk_data->num; i++) { + struct clk_hw *hw = desc->clk_data->hws[i]; + + if (!hw) + continue; + + ret = devm_clk_hw_register(dev, hw); + if (ret) + return dev_err_probe(dev, ret, "failed to register hw of clk%d\n", i); + } + + ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, + desc->clk_data); + if (ret) + return dev_err_probe(dev, ret, "failed to add clock provider\n"); + + return rtk_reset_controller_register(dev, aux_name, regmap); +} +EXPORT_SYMBOL_NS_GPL(rtk_clk_probe, "REALTEK_CLK"); + +MODULE_DESCRIPTION("Realtek clock infrastructure"); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/realtek/common.h b/drivers/clk/realtek/common.h new file mode 100644 index 000000000000..c52fcdbff5ee --- /dev/null +++ b/drivers/clk/realtek/common.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2016-2026 Realtek Semiconductor Corporation + * Author: Cheng-Yu Lee + */ + +#ifndef __CLK_REALTEK_COMMON_H +#define __CLK_REALTEK_COMMON_H + +#include + +#define __clk_regmap_hw(_p) ((_p)->hw) + +struct device; +struct platform_device; +struct regmap; + +struct clk_regmap { + struct clk_hw hw; + struct regmap *regmap; +}; + +struct rtk_clk_desc { + struct clk_hw_onecell_data *clk_data; + struct clk_regmap * const *clks; + size_t num_clks; +}; + +static inline struct clk_regmap *to_clk_regmap(struct clk_hw *hw) +{ + return container_of(hw, struct clk_regmap, hw); +} + +int rtk_clk_probe(struct platform_device *pdev, const struct rtk_clk_desc *desc, + const char *aux_name); + +#endif /* __CLK_REALTEK_COMMON_H */ -- 2.34.1