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Fri, 8 May 2026 19:16:42 +0800 Received: from RTKEXHMBS01.realtek.com.tw (172.21.6.40) by RTKEXHMBS04.realtek.com.tw (10.21.1.54) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Fri, 8 May 2026 19:16:42 +0800 Received: from RTKEXHMBS06.realtek.com.tw (10.21.1.56) by RTKEXHMBS01.realtek.com.tw (172.21.6.40) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.17; Fri, 8 May 2026 19:16:42 +0800 Received: from cn1dhc-k02 (172.21.252.101) by RTKEXHMBS06.realtek.com.tw (10.21.1.56) with Microsoft SMTP Server id 15.2.2562.17 via Frontend Transport; Fri, 8 May 2026 19:16:42 +0800 From: Yu-Chun Lin To: , , , , , , , , CC: , , , , , , , , , Subject: [PATCH v7 04/10] clk: realtek: Add support for phase locked loops (PLLs) Date: Fri, 8 May 2026 19:16:35 +0800 Message-ID: <20260508111641.3192177-5-eleanor.lin@realtek.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20260508111641.3192177-1-eleanor.lin@realtek.com> References: <20260508111641.3192177-1-eleanor.lin@realtek.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260508_121751_323010_92359E86 X-CRM114-Status: GOOD ( 20.17 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Cheng-Yu Lee Provide a full set of PLL operations for programmable PLLs and a read-only variant for fixed or hardware-managed PLLs. Signed-off-by: Cheng-Yu Lee Co-developed-by: Yu-Chun Lin Signed-off-by: Yu-Chun Lin --- drivers/clk/realtek/Makefile | 2 + drivers/clk/realtek/clk-pll.c | 201 +++++++++++++++++++++++++++++++ drivers/clk/realtek/clk-pll.h | 48 ++++++++ drivers/clk/realtek/freq_table.c | 38 ++++++ drivers/clk/realtek/freq_table.h | 16 +++ 5 files changed, 305 insertions(+) create mode 100644 drivers/clk/realtek/clk-pll.c create mode 100644 drivers/clk/realtek/clk-pll.h create mode 100644 drivers/clk/realtek/freq_table.c create mode 100644 drivers/clk/realtek/freq_table.h diff --git a/drivers/clk/realtek/Makefile b/drivers/clk/realtek/Makefile index 377ec776ee47..a89ad77993e9 100644 --- a/drivers/clk/realtek/Makefile +++ b/drivers/clk/realtek/Makefile @@ -2,3 +2,5 @@ obj-$(CONFIG_RTK_CLK_COMMON) += clk-rtk.o clk-rtk-y += common.o +clk-rtk-y += clk-pll.o +clk-rtk-y += freq_table.o diff --git a/drivers/clk/realtek/clk-pll.c b/drivers/clk/realtek/clk-pll.c new file mode 100644 index 000000000000..b63f3aa92d3f --- /dev/null +++ b/drivers/clk/realtek/clk-pll.c @@ -0,0 +1,201 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2024-2026 Realtek Semiconductor Corporation + * Author: Cheng-Yu Lee + */ + +#include +#include +#include +#include "clk-pll.h" + +#define TIMEOUT 2000 + +static inline struct clk_pll *to_clk_pll(struct clk_hw *hw) +{ + struct clk_regmap *clkr = to_clk_regmap(hw); + + return container_of(clkr, struct clk_pll, clkr); +} + +static int wait_freq_ready(struct clk_pll *clkp) +{ + u32 pollval; + + if (!clkp->freq_ready_valid) + return 0; + + return regmap_read_poll_timeout_atomic(clkp->clkr.regmap, clkp->freq_ready_reg, pollval, + (pollval & clkp->freq_ready_mask) == clkp->freq_ready_val, 1, TIMEOUT); +} + +static bool is_power_on(struct clk_pll *clkp) +{ + u32 val; + + if (!clkp->power_reg) + return true; + + if (regmap_read(clkp->clkr.regmap, clkp->power_reg, &val)) + return true; + + return (val & clkp->power_mask) == clkp->power_val_on; +} + +static void clk_pll_disable(struct clk_hw *hw) +{ + struct clk_pll *clkp = to_clk_pll(hw); + unsigned long flags; + + if (!clkp->seq_power_off) + return; + + spin_lock_irqsave(&clkp->lock, flags); + + regmap_multi_reg_write(clkp->clkr.regmap, clkp->seq_power_off, + clkp->num_seq_power_off); + + spin_unlock_irqrestore(&clkp->lock, flags); +} + +static int clk_pll_is_enabled(struct clk_hw *hw) +{ + struct clk_pll *clkp = to_clk_pll(hw); + unsigned long flags; + int ret; + + spin_lock_irqsave(&clkp->lock, flags); + + ret = is_power_on(clkp); + + spin_unlock_irqrestore(&clkp->lock, flags); + + return ret; +} + +static int clk_pll_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + struct clk_pll *clkp = to_clk_pll(hw); + const struct freq_table *ftblv = NULL; + + ftblv = ftbl_find_by_rate(clkp->freq_tbl, req->rate); + if (!ftblv) + return -EINVAL; + + req->rate = ftblv->rate; + + return 0; +} + +static unsigned long clk_pll_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct clk_pll *clkp = to_clk_pll(hw); + const struct freq_table *fv; + unsigned long flags; + u32 freq_val; + + spin_lock_irqsave(&clkp->lock, flags); + + if (regmap_read(clkp->clkr.regmap, clkp->freq_reg, &freq_val)) + return 0; + + freq_val &= clkp->freq_mask; + + fv = ftbl_find_by_val_with_mask(clkp->freq_tbl, clkp->freq_mask, + freq_val); + + spin_unlock_irqrestore(&clkp->lock, flags); + + return fv ? fv->rate : 0; +} + +static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct clk_pll *clkp = to_clk_pll(hw); + const struct freq_table *fv; + unsigned long flags; + int ret; + + fv = ftbl_find_by_rate(clkp->freq_tbl, rate); + if (!fv || fv->rate != rate) + return -EINVAL; + + spin_lock_irqsave(&clkp->lock, flags); + + if (clkp->seq_pre_set_freq) { + ret = regmap_multi_reg_write(clkp->clkr.regmap, clkp->seq_pre_set_freq, + clkp->num_seq_pre_set_freq); + if (ret) + goto unlock; + } + + ret = regmap_update_bits(clkp->clkr.regmap, clkp->freq_reg, + clkp->freq_mask, fv->val); + if (ret) + goto unlock; + + if (clkp->seq_post_set_freq) { + ret = regmap_multi_reg_write(clkp->clkr.regmap, clkp->seq_post_set_freq, + clkp->num_seq_post_set_freq); + if (ret) + goto unlock; + } + + if (is_power_on(clkp)) { + ret = wait_freq_ready(clkp); + if (ret) + goto unlock; + } + +unlock: + spin_unlock_irqrestore(&clkp->lock, flags); + + return ret; +} + +static int clk_pll_enable(struct clk_hw *hw) +{ + struct clk_pll *clkp = to_clk_pll(hw); + unsigned long flags; + int ret = 0; + + if (!clkp->seq_power_on) + return ret; + + spin_lock_irqsave(&clkp->lock, flags); + + if (is_power_on(clkp)) + goto unlock; + + ret = regmap_multi_reg_write(clkp->clkr.regmap, clkp->seq_power_on, + clkp->num_seq_power_on); + if (ret) + goto unlock; + + ret = wait_freq_ready(clkp); + if (ret) + goto unlock; + +unlock: + spin_unlock_irqrestore(&clkp->lock, flags); + + return ret; +} + +const struct clk_ops rtk_clk_pll_ops = { + .enable = clk_pll_enable, + .disable = clk_pll_disable, + .is_enabled = clk_pll_is_enabled, + .recalc_rate = clk_pll_recalc_rate, + .determine_rate = clk_pll_determine_rate, + .set_rate = clk_pll_set_rate, +}; +EXPORT_SYMBOL_NS_GPL(rtk_clk_pll_ops, "REALTEK_CLK"); + +const struct clk_ops rtk_clk_pll_ro_ops = { + .recalc_rate = clk_pll_recalc_rate, +}; +EXPORT_SYMBOL_NS_GPL(rtk_clk_pll_ro_ops, "REALTEK_CLK"); diff --git a/drivers/clk/realtek/clk-pll.h b/drivers/clk/realtek/clk-pll.h new file mode 100644 index 000000000000..237b1d8a2f00 --- /dev/null +++ b/drivers/clk/realtek/clk-pll.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2017-2026 Realtek Semiconductor Corporation + * Author: Cheng-Yu Lee + */ + +#ifndef __CLK_REALTEK_CLK_PLL_H +#define __CLK_REALTEK_CLK_PLL_H + +#include +#include "common.h" +#include "freq_table.h" + +struct reg_sequence; + +struct clk_pll { + struct clk_regmap clkr; + const struct reg_sequence *seq_power_on; + u32 num_seq_power_on; + const struct reg_sequence *seq_power_off; + u32 num_seq_power_off; + const struct reg_sequence *seq_pre_set_freq; + u32 num_seq_pre_set_freq; + const struct reg_sequence *seq_post_set_freq; + u32 num_seq_post_set_freq; + const struct freq_table *freq_tbl; + u32 freq_reg; + u32 freq_mask; + u32 freq_ready_valid; + u32 freq_ready_mask; + u32 freq_ready_reg; + u32 freq_ready_val; + u32 power_reg; + u32 power_mask; + u32 power_val_on; + + /* This lock prevents race conditions when multiple CPUs or contexts + * simultaneously access this PLL's registers during multi-step operations + */ + spinlock_t lock; +}; + +#define __clk_pll_hw(_ptr) __clk_regmap_hw(&(_ptr)->clkr) + +extern const struct clk_ops rtk_clk_pll_ops; +extern const struct clk_ops rtk_clk_pll_ro_ops; + +#endif /* __CLK_REALTEK_CLK_PLL_H */ diff --git a/drivers/clk/realtek/freq_table.c b/drivers/clk/realtek/freq_table.c new file mode 100644 index 000000000000..0ff1e5e79102 --- /dev/null +++ b/drivers/clk/realtek/freq_table.c @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include +#include "freq_table.h" + +#define IS_FREQ_TABLE_END(_f) ((_f)->rate == 0) + +const struct freq_table *ftbl_find_by_rate(const struct freq_table *ftbl, + unsigned long rate) +{ + const struct freq_table *best = NULL; + unsigned long best_rate = 0; + + for (; !IS_FREQ_TABLE_END(ftbl); ftbl++) { + if (ftbl->rate == rate) + return ftbl; + + if (ftbl->rate > rate) + continue; + + if (ftbl->rate > best_rate) { + best_rate = ftbl->rate; + best = ftbl; + } + } + + return best; +} + +const struct freq_table * +ftbl_find_by_val_with_mask(const struct freq_table *ftbl, u32 mask, u32 value) +{ + for (; !IS_FREQ_TABLE_END(ftbl); ftbl++) { + if ((ftbl->val & mask) == (value & mask)) + return ftbl; + } + return NULL; +}; diff --git a/drivers/clk/realtek/freq_table.h b/drivers/clk/realtek/freq_table.h new file mode 100644 index 000000000000..16bf7e3fd489 --- /dev/null +++ b/drivers/clk/realtek/freq_table.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +struct freq_table { + u32 val; + unsigned long rate; +}; + +#define FREQ_TABLE_END \ + { \ + .rate = 0 \ + } + +const struct freq_table *ftbl_find_by_rate(const struct freq_table *ftbl, + unsigned long rate); +const struct freq_table * +ftbl_find_by_val_with_mask(const struct freq_table *ftbl, u32 mask, u32 value); -- 2.34.1