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[47.54.130.67]) by smtp.gmail.com with ESMTPSA id af79cd13be357-907b8d9eed0sm552694685a.19.2026.05.09.10.10.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 09 May 2026 10:10:14 -0700 (PDT) Received: from jgg by wakko with local (Exim 4.97) (envelope-from ) id 1wLlBt-00000001qju-3hnc; Sat, 09 May 2026 14:10:13 -0300 Date: Sat, 9 May 2026 14:10:13 -0300 From: Jason Gunthorpe To: Joonwon Kang Cc: Alexander.Grest@microsoft.com, amhetre@nvidia.com, baolu.lu@linux.intel.com, iommu@lists.linux.dev, joro@8bytes.org, jpb@kernel.org, kees@kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, nicolinc@nvidia.com, praan@google.com, robin.murphy@arm.com, smostafa@google.com, will@kernel.org, jacob.jun.pan@linux.intel.com, easwar.hariharan@linux.microsoft.com, kevin.tian@intel.com Subject: Re: [PATCH RFC] iommu: Enable per-device SSID space for SVA Message-ID: <20260509171013.GF9285@ziepe.ca> References: <20260424133953.GY3611611@ziepe.ca> <20260507095851.3220765-1-joonwonkang@google.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260507095851.3220765-1-joonwonkang@google.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260509_101018_478085_09369590 X-CRM114-Status: GOOD ( 19.36 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, May 07, 2026 at 09:58:51AM +0000, Joonwon Kang wrote: > By "similar instruction" on ARM, I guess you mean ST64BV0, which fetches > the bottom 32 bits data from ACCDATA_EL1. Please let me know if you meant > others as it will matter. If ST64BV0 is supported on ARM, however, it > would mean that ST64B and ST64BV are also supported already according to > the ID_AA64ISAR1_EL1's LS64 field. The latter 2 instructions are just to > atomically store whatever user wants to a memory location without > referring to ACCDATA_EL1 and all the 3 instructions can be run at EL0. So, > the userspace driver would have enough capability to designate arbitrary > PASID as it wants via the latter 2 instructions when communicating with > multiple devices. IDK exactly what ARM did. IIRC on Intel ENQCMD forms a special non-posted write TLP and the device can tell the TLP came from ENQCMD and so it trusts the encoded PASID. ARM has to have done the same thing - allowing anyone to forge the PASID by using a different instruction misses the point of the Intel design. Honestly, I'm not sure why they even implemented it. SMMUv3 can't do the translation scheme required to use ENQCMD from a VM anyhow, so it is pretty useless. > We have multiple processes and a single device, those processes want to > do SVA with the same device, and only one process will do SVA with the > device at a time. Though, the problem occurs even when irrelevant > processes allocate the PASIDs from the global PASID space for their own > irrelevant purposes. The only way to allocate a PASID from the global PASID space is to establish another SVA, so you have multiple devices doing SVA? Jason