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From: Will Deacon <will@kernel.org>
To: linux-arm-kernel@lists.infradead.org
Cc: Will Deacon <will@kernel.org>,
	Catalin Marinas <catalin.marinas@arm.com>,
	Mark Rutland <mark.rutland@arm.com>,
	Marc Zyngier <maz@kernel.org>
Subject: [PATCH] arm64: cpucaps: Keep entries sorted
Date: Tue, 19 May 2026 10:22:42 +0100	[thread overview]
Message-ID: <20260519092243.7278-1-will@kernel.org> (raw)

The cpucaps list is supposed to be sorted, even though the awk script
which processes it doesn't really care. Since this isn't enforced or
relied upon and because the alphabet is hard, the list has gradually
developed an ordering of its own.

Re-sort the file.

Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Reported-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Will Deacon <will@kernel.org>
---

Marc pointed out that HAS_BBML2_NOABORT was in the wrong place but, on
closer inspection, there are a bunch of misplaced entries here. I
honestly don't like the churn of re-sorting it, so an alternative is
to live with it and remove the comment at the top asking people to keep
it sorted it. Any preferences?

 arch/arm64/tools/cpucaps | 28 ++++++++++++++--------------
 1 file changed, 14 insertions(+), 14 deletions(-)

diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps
index 811c2479e82d..0fc05b5026eb 100644
--- a/arch/arm64/tools/cpucaps
+++ b/arch/arm64/tools/cpucaps
@@ -5,6 +5,7 @@
 ALWAYS_BOOT
 ALWAYS_SYSTEM
 BTI
+HAFT
 # Unreliable: use system_supports_32bit_el0() instead.
 HAS_32BIT_EL0_DO_NOT_USE
 HAS_32BIT_EL1
@@ -14,6 +15,7 @@ HAS_ADDRESS_AUTH_ARCH_QARMA5
 HAS_ADDRESS_AUTH_IMP_DEF
 HAS_AMU_EXTN
 HAS_ARMv8_4_TTL
+HAS_BBML2_NOABORT
 HAS_CACHE_DIC
 HAS_CACHE_IDC
 HAS_CNP
@@ -26,41 +28,40 @@ HAS_ECV
 HAS_ECV_CNTPOFF
 HAS_EPAN
 HAS_EVT
-HAS_FPMR
 HAS_FGT
 HAS_FGT2
+HAS_FPMR
 HAS_FPSIMD
 HAS_GCS
 HAS_GENERIC_AUTH
 HAS_GENERIC_AUTH_ARCH_QARMA3
 HAS_GENERIC_AUTH_ARCH_QARMA5
 HAS_GENERIC_AUTH_IMP_DEF
+HAS_GIC_PRIO_MASKING
+HAS_GIC_PRIO_RELAXED_SYNC
 HAS_GICV3_CPUIF
 HAS_GICV5_CPUIF
 HAS_GICV5_LEGACY
-HAS_GIC_PRIO_MASKING
-HAS_GIC_PRIO_RELAXED_SYNC
-HAS_ICH_HCR_EL2_TDIR
 HAS_HCR_NV1
 HAS_HCX
+HAS_ICH_HCR_EL2_TDIR
 HAS_LDAPR
 HAS_LPA2
-HAS_LSE_ATOMICS
 HAS_LS64
 HAS_LS64_V
+HAS_LSE_ATOMICS
 HAS_LSUI
 HAS_MOPS
 HAS_NESTED_VIRT
-HAS_BBML2_NOABORT
 HAS_PAN
 HAS_PMUV3
-HAS_S1PIE
-HAS_S1POE
-HAS_SCTLR2
 HAS_RAS_EXTN
 HAS_RASV1P1_EXTN
 HAS_RNG
+HAS_S1PIE
+HAS_S1POE
 HAS_SB
+HAS_SCTLR2
 HAS_STAGE2_FWB
 HAS_TCR2
 HAS_TIDCP1
@@ -69,7 +70,6 @@ HAS_VA52
 HAS_VIRT_HOST_EXTN
 HAS_WFXT
 HAS_XNX
-HAFT
 HW_DBM
 KVM_HVHE
 KVM_PROTECTED_MODE
@@ -83,10 +83,10 @@ MTE_STORE_ONLY
 SME
 SME_FA64
 SME2
+SPECTRE_BHB
 SPECTRE_V2
 SPECTRE_V3A
 SPECTRE_V4
-SPECTRE_BHB
 SSBS
 SVE
 UNMAP_KERNEL_AT_EL0
@@ -110,9 +110,6 @@ WORKAROUND_4193714
 WORKAROUND_4311569
 WORKAROUND_AMPERE_AC03_CPU_38
 WORKAROUND_AMPERE_AC04_CPU_23
-WORKAROUND_TRBE_OVERWRITE_FILL_MODE
-WORKAROUND_TSB_FLUSH_FAILURE
-WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
 WORKAROUND_CAVIUM_23154
 WORKAROUND_CAVIUM_27456
 WORKAROUND_CAVIUM_30115
@@ -128,3 +125,6 @@ WORKAROUND_REPEAT_TLBI
 WORKAROUND_SPECULATIVE_AT
 WORKAROUND_SPECULATIVE_SSBS
 WORKAROUND_SPECULATIVE_UNPRIV_LOAD
+WORKAROUND_TRBE_OVERWRITE_FILL_MODE
+WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
+WORKAROUND_TSB_FLUSH_FAILURE
-- 
2.54.0.563.g4f69b47b94-goog



             reply	other threads:[~2026-05-19  9:23 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-05-19  9:22 Will Deacon [this message]
2026-05-19  9:53 ` [PATCH] arm64: cpucaps: Keep entries sorted Fuad Tabba
2026-05-19 10:22 ` Marc Zyngier

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