From: Marc Zyngier <maz@kernel.org>
To: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org
Cc: Steffen Eiden <seiden@linux.ibm.com>,
Joey Gouly <joey.gouly@arm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Oliver Upton <oupton@kernel.org>,
Zenghui Yu <yuzenghui@huawei.com>,
Sascha Bischoff <sascha.bischoff@arm.com>
Subject: [PATCH v2 00/18] KVM: arm64: vgic-v5 fixes for 7.2
Date: Wed, 20 May 2026 10:19:31 +0100 [thread overview]
Message-ID: <20260520091949.542365-1-maz@kernel.org> (raw)
Having completely missed the 7.1 window, this is a repost of this
series cleaning-up the vgic-v5 PPI support now targeting 7.2.
Not a lot has changed since v1 [1], only the documentation typo
spotted by our eagle-eyed Joey.
[1] https://lore.kernel.org/r/20260415115559.2227718-1-maz@kernel.org
Marc Zyngier (9):
KVM: arm64: vgic-v5: Add for_each_visible_v5_ppi() iterator
KVM: arm64: vgic-v5: Move PPI caps into kvm_vgic_global_state
KVM: arm64: vgic-v5: Remove use of __assign_bit() with a constant
KVM: arm64: vgic-v5: Drop pointless ARM64_HAS_GICV5_CPUIF check
KVM: arm64: vgic: Constify struct irq_ops usage
KVM: arm64: vgic: Consolidate vgic_allocate_private_irqs_locked()
KVM: arm64: vgic-v5: Drop defensive checks from
vgic_v5_ppi_queue_irq_unlock()
KVM: arm64: vgic: Rationalise per-CPU irq accessor
KVM: arm64: vgic-v5: Limit support to 64 PPIs
Sascha Bischoff (9):
KVM: arm64: vgic-v5: Add missing trap handing for NV triage
KVM: arm64: vgic-v5: Atomically assign bits to PPI DVI bitmap
KVM: arm64: selftests: Add missing GIC CDEN to no-vgic-v5 selftest
KVM: arm64: selftests: Cleanup unused vars in GICv5 PPI selftest
KVM: arm64: selftests: Improve error handling for GICv5 PPI selftest
Documentation: KVM: Fix typos in VGICv5 documentation
Documentation: KVM: Clarify that PMU_V3_IRQ IntID requirements for
GICv5
irqchip/gic-v5: Immediately exec priority drop following activate
KVM: arm64: Fix arch timer interrupts for GICv3-on-GICv5 guests
.../virt/kvm/devices/arm-vgic-v5.rst | 6 +-
Documentation/virt/kvm/devices/vcpu.rst | 7 +-
arch/arm64/kvm/arch_timer.c | 31 +++----
arch/arm64/kvm/emulate-nested.c | 8 ++
arch/arm64/kvm/hyp/vgic-v5-sr.c | 82 ++++---------------
arch/arm64/kvm/sys_regs.c | 19 ++---
arch/arm64/kvm/vgic/vgic-init.c | 45 ++++------
arch/arm64/kvm/vgic/vgic-kvm-device.c | 9 +-
arch/arm64/kvm/vgic/vgic-v5.c | 51 ++++--------
arch/arm64/kvm/vgic/vgic.c | 27 +++---
arch/arm64/kvm/vgic/vgic.h | 3 +
drivers/irqchip/irq-gic-v5.c | 13 +--
include/kvm/arm_vgic.h | 19 +++--
tools/testing/selftests/kvm/arm64/no-vgic.c | 1 +
tools/testing/selftests/kvm/arm64/vgic_v5.c | 10 +--
15 files changed, 132 insertions(+), 199 deletions(-)
--
2.47.3
next reply other threads:[~2026-05-20 9:20 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-20 9:19 Marc Zyngier [this message]
2026-05-20 9:19 ` [PATCH v2 01/18] KVM: arm64: vgic-v5: Add for_each_visible_v5_ppi() iterator Marc Zyngier
2026-05-20 9:19 ` [PATCH v2 02/18] KVM: arm64: vgic-v5: Move PPI caps into kvm_vgic_global_state Marc Zyngier
2026-05-20 9:19 ` [PATCH v2 03/18] KVM: arm64: vgic-v5: Remove use of __assign_bit() with a constant Marc Zyngier
2026-05-20 13:26 ` Joey Gouly
2026-05-20 9:19 ` [PATCH v2 04/18] KVM: arm64: vgic-v5: Drop pointless ARM64_HAS_GICV5_CPUIF check Marc Zyngier
2026-05-20 9:19 ` [PATCH v2 05/18] KVM: arm64: vgic: Constify struct irq_ops usage Marc Zyngier
2026-05-20 9:19 ` [PATCH v2 06/18] KVM: arm64: vgic: Consolidate vgic_allocate_private_irqs_locked() Marc Zyngier
2026-05-20 9:19 ` [PATCH v2 07/18] KVM: arm64: vgic-v5: Drop defensive checks from vgic_v5_ppi_queue_irq_unlock() Marc Zyngier
2026-05-20 9:19 ` [PATCH v2 08/18] KVM: arm64: vgic: Rationalise per-CPU irq accessor Marc Zyngier
2026-05-20 9:19 ` [PATCH v2 09/18] KVM: arm64: vgic-v5: Limit support to 64 PPIs Marc Zyngier
2026-05-20 9:19 ` [PATCH v2 10/18] KVM: arm64: vgic-v5: Add missing trap handing for NV triage Marc Zyngier
2026-05-20 13:54 ` Joey Gouly
2026-05-20 9:19 ` [PATCH v2 11/18] KVM: arm64: vgic-v5: Atomically assign bits to PPI DVI bitmap Marc Zyngier
2026-05-20 9:19 ` [PATCH v2 12/18] KVM: arm64: selftests: Add missing GIC CDEN to no-vgic-v5 selftest Marc Zyngier
2026-05-20 9:19 ` [PATCH v2 13/18] KVM: arm64: selftests: Cleanup unused vars in GICv5 PPI selftest Marc Zyngier
2026-05-20 9:19 ` [PATCH v2 14/18] KVM: arm64: selftests: Improve error handling for " Marc Zyngier
2026-05-20 9:19 ` [PATCH v2 15/18] Documentation: KVM: Fix typos in VGICv5 documentation Marc Zyngier
2026-05-20 9:19 ` [PATCH v2 16/18] Documentation: KVM: Clarify that PMU_V3_IRQ IntID requirements for GICv5 Marc Zyngier
2026-05-20 9:19 ` [PATCH v2 17/18] irqchip/gic-v5: Immediately exec priority drop following activate Marc Zyngier
2026-05-20 9:19 ` [PATCH v2 18/18] KVM: arm64: Fix arch timer interrupts for GICv3-on-GICv5 guests Marc Zyngier
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20260520091949.542365-1-maz@kernel.org \
--to=maz@kernel.org \
--cc=joey.gouly@arm.com \
--cc=kvmarm@lists.linux.dev \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=oupton@kernel.org \
--cc=sascha.bischoff@arm.com \
--cc=seiden@linux.ibm.com \
--cc=suzuki.poulose@arm.com \
--cc=yuzenghui@huawei.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox