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From: Bjorn Helgaas <helgaas@kernel.org>
To: Nicolin Chen <nicolinc@nvidia.com>
Cc: Jason Gunthorpe <jgg@nvidia.com>,
	will@kernel.org, robin.murphy@arm.com, bhelgaas@google.com,
	joro@8bytes.org, praan@google.com, baolu.lu@linux.intel.com,
	kevin.tian@intel.com, miko.lenczewski@arm.com,
	linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev,
	linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org,
	dan.j.williams@intel.com, jonathan.cameron@huawei.com,
	vsethi@nvidia.com, linux-cxl@vger.kernel.org, nirmoyd@nvidia.com
Subject: Re: [PATCH v4 1/3] PCI: Allow ATS to be always on for CXL.cache capable devices
Date: Wed, 20 May 2026 12:47:58 -0500	[thread overview]
Message-ID: <20260520174758.GA66039@bhelgaas> (raw)
In-Reply-To: <ag3vb4SWIfuw++vp@Asurada-Nvidia>

On Wed, May 20, 2026 at 10:29:19AM -0700, Nicolin Chen wrote:
> On Wed, May 20, 2026 at 11:20:43AM -0300, Jason Gunthorpe wrote:
> > On Tue, May 19, 2026 at 06:04:18PM -0700, Nicolin Chen wrote:
> > 
> > > > Yeah, that's fair, so let's rename it to 
> > > > 
> > > > pci_translated_required()
> > > > 
> > > > ie the device requires translated requests to function. This is what
> > > > CXL.cache implies (IIRC I was told the spec specifically says this)
> > > > 
> > > > Requiring translated requests implies you have to enable ATS in the
> > > > system.
> > > 
> > > Perhaps we could let IOMMU drivers check:
> > >   pci_cxl_is_cache_capable() || pci_dev_specific_is_pre_cxl()
> > > directly?
> > 
> > I'd rather have a single function.
> 
> OK. Can we use pci_ats_required()?
> 
> CXL spec explicitly used "ATS" when stating the requirement of
> CXL.cache). And it'd fit into the existing pci_ats_ functions.

OK by me.

You already have a comment in the code about the CXL.cache
requirement; thanks for that.

I don't know enough about CXL to know what's behind the ATS
requirement.  It sounds like it's more than a simple performance
optimization.  If you happen to know the reason, it might be worth
a short comment about that too.

Please add a one-line comment in the code about why we check
Cache_Capable instead of Cache_Enable, i.e., even if CXL.cache is not
enabled now, it may be enabled later.

Bjorn


  reply	other threads:[~2026-05-20 17:48 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-04-27  5:53 [PATCH v4 0/3] Allow ATS to be always on for certain ATS-capable devices Nicolin Chen
2026-04-27  5:54 ` [PATCH v4 1/3] PCI: Allow ATS to be always on for CXL.cache capable devices Nicolin Chen
2026-04-27 16:31   ` Dave Jiang
2026-04-30 21:41   ` Dan Williams (nvidia)
2026-04-30 23:28     ` Nicolin Chen
2026-05-01 23:27       ` Dan Williams (nvidia)
2026-05-01 23:46         ` Jason Gunthorpe
2026-05-02  0:19           ` Dan Williams (nvidia)
2026-05-19 19:36   ` Bjorn Helgaas
2026-05-19 22:23     ` Jason Gunthorpe
2026-05-19 23:48       ` Bjorn Helgaas
2026-05-20  0:05         ` Jason Gunthorpe
2026-05-20  1:04           ` Nicolin Chen
2026-05-20 14:20             ` Jason Gunthorpe
2026-05-20 17:29               ` Nicolin Chen
2026-05-20 17:47                 ` Bjorn Helgaas [this message]
2026-05-20 17:56                   ` Jason Gunthorpe
2026-05-20 13:12   ` Yi Liu
2026-05-20 14:34     ` Jason Gunthorpe
2026-04-27  5:54 ` [PATCH v4 2/3] PCI: Allow ATS to be always on for pre-CXL devices Nicolin Chen
2026-04-27 16:32   ` Dave Jiang
2026-05-20 13:12   ` Yi Liu
2026-05-20 17:50   ` Bjorn Helgaas
2026-05-20 17:53     ` Jason Gunthorpe
2026-04-27  5:54 ` [PATCH v4 3/3] iommu/arm-smmu-v3: Allow ATS to be always on Nicolin Chen
2026-04-27 16:37   ` Dave Jiang

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