From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7F693CD5BB0 for ; Fri, 22 May 2026 10:18:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=qjEAnLVJmpzdK57mtuR3mw3KcIqIuL7gz+T4jtEwSJo=; b=TpfKTVi0B1wKb24/JalIQz8+kY 56x65+0H0zGE4UKyaOb2zp955yDITNfGPNTM6AXMDZ3PjDqGZZ8iBw0jh5MXj1U4r+4vsroR3P5ES deDTU7eC/b8U99LeqN7pjG0OYSYt9zWOb5RtUQs9aTuBSRsAtvgHf99p2yGGzcM0lObGYDcKfUyor m+Ds1zHP9WFueRp9zjx4CJakyTJTjACmrZ1pYj10KpJOUGd5q2YdGeoqkb3+tByZpqFA3vr1r3BuQ heaR4Iaxj6MSf1696piJhW6NwS7UB8YAwrOM9JdrmYiM2EXbHWSr1Z+TeqkminJHMsJGn22gQeSq3 B6pGsbmQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.99.1 #2 (Red Hat Linux)) id 1wQMxm-0000000AUAj-21TX; Fri, 22 May 2026 10:18:42 +0000 Received: from leonov.paulk.fr ([185.233.101.22]) by bombadil.infradead.org with esmtps (Exim 4.99.1 #2 (Red Hat Linux)) id 1wQMxi-0000000AU5S-2JwU for linux-arm-kernel@lists.infradead.org; Fri, 22 May 2026 10:18:39 +0000 Received: from laika.paulk.fr (12.234.24.109.rev.sfr.net [109.24.234.12]) by leonov.paulk.fr (Postfix) with ESMTPS id 7FD9037002A0 for ; Fri, 22 May 2026 10:18:19 +0000 (UTC) Received: by laika.paulk.fr (Postfix, from userid 65534) id EADF8B408D7; Fri, 22 May 2026 10:18:18 +0000 (UTC) Received: from shepard (unknown [192.168.1.65]) by laika.paulk.fr (Postfix) with ESMTP id BBEE9B408D6; Fri, 22 May 2026 10:17:18 +0000 (UTC) From: Paul Kocialkowski To: devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Nicolas Dufresne , Benjamin Gaignard , Philipp Zabel , Mauro Carvalho Chehab , Hans Verkuil , Marco Felsch , Michael Tretter , Paul Kocialkowski Subject: [PATCH 13/14] media: verilisicon: imx8m: Add support for the VC8000E on i.MX8MP Date: Fri, 22 May 2026 12:16:52 +0200 Message-ID: <20260522101653.2565125-14-paulk@sys-base.io> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260522101653.2565125-1-paulk@sys-base.io> References: <20260522101653.2565125-1-paulk@sys-base.io> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260522_031838_932212_45E5052C X-CRM114-Status: GOOD ( 13.68 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add the required platform-specific bits for driving the VC8000E found on the NXP i.MX8MP SoC. Signed-off-by: Paul Kocialkowski Signed-off-by: Marco Felsch Co-authored-by: Marco Felsch --- .../media/platform/verisilicon/hantro_drv.c | 1 + .../media/platform/verisilicon/hantro_hw.h | 1 + .../media/platform/verisilicon/imx8m_vpu_hw.c | 113 ++++++++++++++++++ 3 files changed, 115 insertions(+) diff --git a/drivers/media/platform/verisilicon/hantro_drv.c b/drivers/media/platform/verisilicon/hantro_drv.c index 2de27f0a2be0..540e3b647fe4 100644 --- a/drivers/media/platform/verisilicon/hantro_drv.c +++ b/drivers/media/platform/verisilicon/hantro_drv.c @@ -874,6 +874,7 @@ static const struct of_device_id of_hantro_match[] = { #endif #ifdef CONFIG_VIDEO_HANTRO_IMX8M { .compatible = "nxp,imx8mm-vpu-g1", .data = &imx8mm_vpu_g1_variant, }, + { .compatible = "nxp,imx8mp-vpu-vc8000e", .data = &imx8mp_vpu_vc8000e_variant, }, { .compatible = "nxp,imx8mq-vpu", .data = &imx8mq_vpu_variant, }, { .compatible = "nxp,imx8mq-vpu-g1", .data = &imx8mq_vpu_g1_variant }, { .compatible = "nxp,imx8mq-vpu-g2", .data = &imx8mq_vpu_g2_variant }, diff --git a/drivers/media/platform/verisilicon/hantro_hw.h b/drivers/media/platform/verisilicon/hantro_hw.h index a0c752ef44dd..5f79fb401da5 100644 --- a/drivers/media/platform/verisilicon/hantro_hw.h +++ b/drivers/media/platform/verisilicon/hantro_hw.h @@ -420,6 +420,7 @@ enum hantro_enc_fmt { ROCKCHIP_VPU_ENC_FMT_UYVY422 = 3, }; +extern const struct hantro_variant imx8mp_vpu_vc8000e_variant; extern const struct hantro_variant imx8mm_vpu_g1_variant; extern const struct hantro_variant imx8mq_vpu_g1_variant; extern const struct hantro_variant imx8mq_vpu_g2_variant; diff --git a/drivers/media/platform/verisilicon/imx8m_vpu_hw.c b/drivers/media/platform/verisilicon/imx8m_vpu_hw.c index f9f276385c11..50ce4a5f979d 100644 --- a/drivers/media/platform/verisilicon/imx8m_vpu_hw.c +++ b/drivers/media/platform/verisilicon/imx8m_vpu_hw.c @@ -234,6 +234,96 @@ static const struct hantro_fmt imx8m_vpu_g2_dec_fmts[] = { }, }; +static const struct hantro_fmt imx8mp_vc8000e_fmts[] = { + { + .fourcc = V4L2_PIX_FMT_YUV420M, + .codec_mode = HANTRO_MODE_NONE, + .enc_fmt = ROCKCHIP_VPU_ENC_FMT_YUV420P, + .frmsize = { + .min_width = FMT_MIN_WIDTH, + .max_width = FMT_FHD_WIDTH, + .step_width = MB_DIM, + .min_height = FMT_MIN_HEIGHT, + .max_height = FMT_FHD_HEIGHT, + /* TODO: implement dummy reads to relax size restrictions */ + .step_height = 64, + }, + }, { + .fourcc = V4L2_PIX_FMT_YUV420, + .codec_mode = HANTRO_MODE_NONE, + .enc_fmt = ROCKCHIP_VPU_ENC_FMT_YUV420P, + .frmsize = { + .min_width = FMT_MIN_WIDTH, + .max_width = FMT_FHD_WIDTH, + .step_width = MB_DIM, + .min_height = FMT_MIN_HEIGHT, + .max_height = FMT_FHD_HEIGHT, + /* TODO: implement dummy reads to relax size restrictions */ + .step_height = 64, + }, + }, { + .fourcc = V4L2_PIX_FMT_NV12M, + .codec_mode = HANTRO_MODE_NONE, + .enc_fmt = ROCKCHIP_VPU_ENC_FMT_YUV420SP, + .frmsize = { + .min_width = FMT_MIN_WIDTH, + .max_width = FMT_FHD_WIDTH, + .step_width = MB_DIM, + .min_height = FMT_MIN_HEIGHT, + .max_height = FMT_FHD_HEIGHT, + .step_height = MB_DIM, + }, + }, { + .fourcc = V4L2_PIX_FMT_NV12, + .codec_mode = HANTRO_MODE_NONE, + .enc_fmt = ROCKCHIP_VPU_ENC_FMT_YUV420SP, + .frmsize = { + .min_width = FMT_MIN_WIDTH, + .max_width = FMT_FHD_WIDTH, + .step_width = MB_DIM, + .min_height = FMT_MIN_HEIGHT, + .max_height = FMT_FHD_HEIGHT, + .step_height = MB_DIM, + }, + }, { + .fourcc = V4L2_PIX_FMT_YUYV, + .codec_mode = HANTRO_MODE_NONE, + .enc_fmt = ROCKCHIP_VPU_ENC_FMT_YUYV422, + .frmsize = { + .min_width = FMT_MIN_WIDTH, + .max_width = FMT_FHD_WIDTH, + .step_width = MB_DIM, + .min_height = FMT_MIN_HEIGHT, + .max_height = FMT_FHD_HEIGHT, + .step_height = MB_DIM, + }, + }, { + .fourcc = V4L2_PIX_FMT_UYVY, + .codec_mode = HANTRO_MODE_NONE, + .enc_fmt = ROCKCHIP_VPU_ENC_FMT_UYVY422, + .frmsize = { + .min_width = FMT_MIN_WIDTH, + .max_width = FMT_FHD_WIDTH, + .step_width = MB_DIM, + .min_height = FMT_MIN_HEIGHT, + .max_height = FMT_FHD_HEIGHT, + .step_height = MB_DIM, + }, + }, { + .fourcc = V4L2_PIX_FMT_H264_SLICE, + .codec_mode = HANTRO_MODE_H264_ENC, + .max_depth = 2, + .frmsize = { + .min_width = FMT_MIN_WIDTH, + .max_width = FMT_FHD_WIDTH, + .step_width = MB_DIM, + .min_height = FMT_MIN_HEIGHT, + .max_height = FMT_FHD_HEIGHT, + .step_height = MB_DIM, + }, + }, +}; + static int imx8mq_vpu_hw_init(struct hantro_dev *vpu) { vpu->ctrl_base = vpu->reg_bases[vpu->variant->num_regs - 1]; @@ -305,6 +395,15 @@ static const struct hantro_codec_ops imx8mq_vpu_g2_codec_ops[] = { }, }; +static const struct hantro_codec_ops imx8mp_vpu_vc8000e_codec_ops[] = { + [HANTRO_MODE_H264_ENC] = { + .run = hantro_vc8000e_h264_enc_run, + .done = hantro_vc8000e_h264_enc_done, + .init = hantro_vc8000e_h264_enc_init, + .exit = hantro_vc8000e_h264_enc_exit, + }, +}; + /* * VPU variants. */ @@ -317,6 +416,10 @@ static const struct hantro_irq imx8mq_g2_irqs[] = { { "g2", hantro_g2_irq }, }; +static const struct hantro_irq imx8mp_vc8000e_irqs[] = { + { "vc8000e", hantro_vc8000e_irq }, +}; + static const char * const imx8mq_clk_names[] = { "g1", "g2", "bus" }; static const char * const imx8mq_reg_names[] = { "g1", "g2", "ctrl" }; static const char * const imx8mq_g1_clk_names[] = { "g1" }; @@ -382,3 +485,13 @@ const struct hantro_variant imx8mm_vpu_g1_variant = { .clk_names = imx8mq_g1_clk_names, .num_clocks = ARRAY_SIZE(imx8mq_g1_clk_names), }; + +const struct hantro_variant imx8mp_vpu_vc8000e_variant = { + .enc_fmts = imx8mp_vc8000e_fmts, + .num_enc_fmts = ARRAY_SIZE(imx8mp_vc8000e_fmts), + .codec = HANTRO_H264_ENCODER, + .codec_ops = imx8mp_vpu_vc8000e_codec_ops, + .irqs = imx8mp_vc8000e_irqs, + .num_irqs = ARRAY_SIZE(imx8mp_vc8000e_irqs), + .num_clocks = 1, +}; -- 2.53.0