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The platform specific changes are integrated in the mipi-i3c-hci driver using existing quirks. I3C in master mode supports up to 12.5MHz, SDR mode data transfer in mixed bus mode (I2C and I3C target devices on same i3c bus). Please refer to the individual patches for changelogs. Durai Manickam KR (2): clk: at91: sama7d65: add peripheral clock for I3C ARM: dts: microchip: add I3C controller Manikandan Muralidharan (3): dt-bindings: i3c: mipi-i3c-hci: add Microchip SAMA7D65 compatible i3c: mipi-i3c-hci: add microchip sama7d65 SoC compatible with the required quirk ARM: configs: at91: sama7: add sama7d65 i3c-hci .../devicetree/bindings/i3c/mipi-i3c-hci.yaml | 27 ++++++++++++++++--- arch/arm/boot/dts/microchip/sama7d65.dtsi | 8 ++++++ arch/arm/configs/sama7_defconfig | 2 ++ drivers/clk/at91/sama7d65.c | 1 + drivers/i3c/master/mipi-i3c-hci/core.c | 10 +++++++ 5 files changed, 44 insertions(+), 4 deletions(-) -- 2.25.1