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X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The bootph-all flag was introduced in dt-schema (dtschema/schemas/bootph.yaml) to define node usage across different boot phases. To ensure SD boot, timer, gpio, syscfg, clock and uart nodes need to be present in all boot stages, so add missing bootph-all phase flag to these nodes to support SD boot. Signed-off-by: Patrice Chotard --- arch/arm/boot/dts/st/stm32429i-eval.dts | 80 ++++++++++++++++++++++++++++++++ arch/arm/boot/dts/st/stm32f429-disco.dts | 80 ++++++++++++++++++++++++++++++++ arch/arm/boot/dts/st/stm32f469-disco.dts | 72 ++++++++++++++++++++++++++++ 3 files changed, 232 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32429i-eval.dts b/arch/arm/boot/dts/st/stm32429i-eval.dts index f4b1c4eb64f2..8a08b9f6b837 100644 --- a/arch/arm/boot/dts/st/stm32429i-eval.dts +++ b/arch/arm/boot/dts/st/stm32429i-eval.dts @@ -188,6 +188,15 @@ adc3: adc@200 { &clk_hse { clock-frequency = <25000000>; + bootph-all; +}; + +&clk_lse { + bootph-all; +}; + +&clk_i2s_ckin { + bootph-all; }; &crc { @@ -209,6 +218,50 @@ dcmi_0: endpoint { }; }; +&gpioa { + bootph-all; +}; + +&gpiob { + bootph-all; +}; + +&gpioc { + bootph-all; +}; + +&gpiod { + bootph-all; +}; + +&gpioe { + bootph-all; +}; + +&gpiof { + bootph-all; +}; + +&gpiog { + bootph-all; +}; + +&gpioh { + bootph-all; +}; + +&gpioi { + bootph-all; +}; + +&gpioj { + bootph-all; +}; + +&gpiok { + bootph-all; +}; + &i2c1 { pinctrl-0 = <&i2c1_pins>; pinctrl-names = "default"; @@ -278,6 +331,18 @@ phy1: ethernet-phy@1 { }; }; +&pinctrl { + bootph-all; +}; + +&pwrcfg { + bootph-all; +}; + +&rcc { + bootph-all; +}; + &rtc { status = "okay"; }; @@ -293,6 +358,10 @@ &sdio { max-frequency = <12500000>; }; +&syscfg { + bootph-all; +}; + &timers1 { status = "okay"; @@ -325,6 +394,7 @@ &timers5 { /* Override timer5 to act as clockevent */ compatible = "st,stm32-timer"; interrupts = <50>; + bootph-all; status = "okay"; /delete-property/#address-cells; /delete-property/#size-cells; @@ -339,6 +409,16 @@ &usart1 { status = "okay"; }; +&usart1_pins_a { + bootph-all; + pins1 { + bootph-all; + }; + pins2 { + bootph-all; + }; +}; + &usbotg_hs { dr_mode = "host"; phys = <&usbotg_hs_phy>; diff --git a/arch/arm/boot/dts/st/stm32f429-disco.dts b/arch/arm/boot/dts/st/stm32f429-disco.dts index ded369abee4f..047845ab3d5f 100644 --- a/arch/arm/boot/dts/st/stm32f429-disco.dts +++ b/arch/arm/boot/dts/st/stm32f429-disco.dts @@ -113,12 +113,65 @@ vcc5v_otg: vcc5v-otg-regulator { &clk_hse { clock-frequency = <8000000>; + bootph-all; +}; + +&clk_lse { + bootph-all; +}; + +&clk_i2s_ckin { + bootph-all; }; &crc { status = "okay"; }; +&gpioa { + bootph-all; +}; + +&gpiob { + bootph-all; +}; + +&gpioc { + bootph-all; +}; + +&gpiod { + bootph-all; +}; + +&gpioe { + bootph-all; +}; + +&gpiof { + bootph-all; +}; + +&gpiog { + bootph-all; +}; + +&gpioh { + bootph-all; +}; + +&gpioi { + bootph-all; +}; + +&gpioj { + bootph-all; +}; + +&gpiok { + bootph-all; +}; + &i2c3 { pinctrl-names = "default"; pinctrl-0 = <&i2c3_pins>; @@ -176,6 +229,18 @@ ltdc_out_rgb: endpoint { }; }; +&pinctrl { + bootph-all; +}; + +&pwrcfg { + bootph-all; +}; + +&rcc { + bootph-all; +}; + &rtc { assigned-clocks = <&rcc 1 CLK_RTC>; assigned-clock-parents = <&rcc 1 CLK_LSI>; @@ -216,10 +281,15 @@ panel_in_rgb: endpoint { }; }; +&syscfg { + bootph-all; +}; + &timers5 { /* Override timer5 to act as clockevent */ compatible = "st,stm32-timer"; interrupts = <50>; + bootph-all; status = "okay"; /delete-property/#address-cells; /delete-property/#size-cells; @@ -234,6 +304,16 @@ &usart1 { status = "okay"; }; +&usart1_pins_a { + bootph-all; + pins1 { + bootph-all; + }; + pins2 { + bootph-all; + }; +}; + &usbotg_hs { compatible = "st,stm32f4x9-fsotg"; dr_mode = "host"; diff --git a/arch/arm/boot/dts/st/stm32f469-disco.dts b/arch/arm/boot/dts/st/stm32f469-disco.dts index 943afba06b5f..ecd33d6003b3 100644 --- a/arch/arm/boot/dts/st/stm32f469-disco.dts +++ b/arch/arm/boot/dts/st/stm32f469-disco.dts @@ -181,7 +181,52 @@ dsi_panel_in: endpoint { }; }; +&gpioa { + bootph-all; +}; + +&gpiob { + bootph-all; +}; + +&gpioc { + bootph-all; +}; + +&gpiod { + bootph-all; +}; + +&gpioe { + bootph-all; +}; + +&gpiof { + bootph-all; +}; + +&gpiog { + bootph-all; +}; + +&gpioh { + bootph-all; +}; + +&gpioi { + bootph-all; +}; + +&gpioj { + bootph-all; +}; + +&gpiok { + bootph-all; +}; + <dc { + bootph-all; status = "okay"; port { @@ -191,10 +236,26 @@ ltdc_out_dsi: endpoint { }; }; +&pinctrl { + bootph-all; +}; + +&pwrcfg { + bootph-all; +}; + +&rcc { + bootph-all; +}; + &rtc { status = "okay"; }; +&syscfg { + bootph-all; +}; + &timers1 { status = "okay"; @@ -238,6 +299,7 @@ &timers5 { /* Override timer5 to act as clockevent */ compatible = "st,stm32-timer"; interrupts = <50>; + bootph-all; status = "okay"; /delete-property/#address-cells; /delete-property/#size-cells; @@ -252,6 +314,16 @@ &usart3 { status = "okay"; }; +&usart3_pins_a { + bootph-all; + pins1 { + bootph-all; + }; + pins2 { + bootph-all; + }; +}; + &usbotg_fs { dr_mode = "host"; pinctrl-0 = <&usbotg_fs_pins_a>; -- 2.43.0