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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: OaRbRasEgX/xxQbNW50G8m6HnUOL3moyfSrkitrdnr3SE6nZCTWPz6bwEVn81Fxz+xGevk8ZT115M6b4koUf1LmweHB1/57ODKpiVsEqgY74UG+UYT5zEWY2+stOAs6GTjrTyUJ0fTe+aXDWCRIzkC9xLn7lQ3s00nbAhBRhvm53U1o7AUljou06M6TNVBFxZtBcBNDs5fklbsYWjxlzqPY3lVNB9F0+ksYo+t+ihMYafhwmPTMQX3E/lUp94vOOw8DqFdt1kvYac0bZx5cmRurf9bB8TW7bzy/SD5RaR9Yx78DTKqvqjaburLsG2LvLf0QMtRScIRTfnLrSJueafq5FAt7JuMxufgkPIz2w/xEZ0GcwP5vxi6MixMXLmcGYyYb3ClgEvPhWRC73kBhOZmb2LP5s+Z/Ulj/T7qAcuOti3wjlmS1pDKaiIWnLer5X X-OriginatorOrg: foss.st.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 May 2026 09:26:45.7279 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a3506d06-e7bb-4420-09c0-08debb08e7e8 X-MS-Exchange-CrossTenant-Id: 75e027c9-20d5-47d5-b82f-77d7cd041e8f X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=75e027c9-20d5-47d5-b82f-77d7cd041e8f;Ip=[164.130.1.60];Helo=[smtpO365.st.com] X-MS-Exchange-CrossTenant-AuthSource: AMS1EPF00000091.eurprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0PR10MB3186 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260526_022652_978672_37A52232 X-CRM114-Status: GOOD ( 11.23 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The bootph-all flag was introduced in dt-schema (dtschema/schemas/bootph.yaml) to define node usage across different boot phases. To ensure SD boot, timer, gpio, syscfg, clock and uart nodes need to be present in all boot stages, so add missing bootph-all phase flag to these nodes to support SD boot. Signed-off-by: Patrice Chotard --- arch/arm/boot/dts/st/stm32746g-eval.dts | 10 +++++ arch/arm/boot/dts/st/stm32f746-disco.dts | 75 +++++++++++++++++++++++++++++++ arch/arm/boot/dts/st/stm32f746.dtsi | 2 +- arch/arm/boot/dts/st/stm32f769-disco.dts | 76 ++++++++++++++++++++++++++++++-- 4 files changed, 158 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/st/stm32746g-eval.dts b/arch/arm/boot/dts/st/stm32746g-eval.dts index 6772c1f9d03e..d66b670de6f2 100644 --- a/arch/arm/boot/dts/st/stm32746g-eval.dts +++ b/arch/arm/boot/dts/st/stm32746g-eval.dts @@ -226,6 +226,16 @@ &usart1 { status = "okay"; }; +&usart1_pins_a { + bootph-all; + pins1 { + bootph-all; + }; + pins2 { + bootph-all; + }; +}; + &usbotg_hs { dr_mode = "otg"; phys = <&usbotg_hs_phy>; diff --git a/arch/arm/boot/dts/st/stm32f746-disco.dts b/arch/arm/boot/dts/st/stm32f746-disco.dts index 61ca41ea523e..5db37bbe6c2a 100644 --- a/arch/arm/boot/dts/st/stm32f746-disco.dts +++ b/arch/arm/boot/dts/st/stm32f746-disco.dts @@ -150,6 +150,51 @@ panel_in_rgb: endpoint { &clk_hse { clock-frequency = <25000000>; + bootph-all; +}; + +&gpioa { + bootph-all; +}; + +&gpiob { + bootph-all; +}; + +&gpioc { + bootph-all; +}; + +&gpiod { + bootph-all; +}; + +&gpioe { + bootph-all; +}; + +&gpiof { + bootph-all; +}; + +&gpiog { + bootph-all; +}; + +&gpioh { + bootph-all; +}; + +&gpioi { + bootph-all; +}; + +&gpioj { + bootph-all; +}; + +&gpiok { + bootph-all; }; &i2c1 { @@ -179,6 +224,7 @@ touchscreen@38 { <dc { pinctrl-0 = <<dc_pins_a>; pinctrl-names = "default"; + bootph-all; status = "okay"; port { @@ -188,6 +234,22 @@ ltdc_out_rgb: endpoint { }; }; +&pinctrl { + bootph-all; +}; + +&pwrcfg { + bootph-all; +}; + +&rcc { + bootph-all; +}; + +&soc { + bootph-all; +}; + &sdio1 { status = "okay"; vmmc-supply = <&vcc_3v3>; @@ -203,6 +265,7 @@ &timers5 { /* Override timer5 to act as clockevent */ compatible = "st,stm32-timer"; interrupts = <50>; + bootph-all; status = "okay"; /delete-property/#address-cells; /delete-property/#size-cells; @@ -214,9 +277,21 @@ &timers5 { &usart1 { pinctrl-0 = <&usart1_pins_b>; pinctrl-names = "default"; + bootph-all; status = "okay"; }; + +&usart1_pins_b { + bootph-all; + pins1 { + bootph-all; + }; + pins2 { + bootph-all; + }; +}; + &usbotg_fs { dr_mode = "host"; pinctrl-0 = <&usbotg_fs_pins_a>; diff --git a/arch/arm/boot/dts/st/stm32f746.dtsi b/arch/arm/boot/dts/st/stm32f746.dtsi index 208f8c6dfc9d..1fede5bdc347 100644 --- a/arch/arm/boot/dts/st/stm32f746.dtsi +++ b/arch/arm/boot/dts/st/stm32f746.dtsi @@ -75,7 +75,7 @@ clk_i2s_ckin: clk-i2s-ckin { }; }; - soc { + soc: soc { timers2: timers@40000000 { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/st/stm32f769-disco.dts b/arch/arm/boot/dts/st/stm32f769-disco.dts index e5854fa1071b..7338e78847b6 100644 --- a/arch/arm/boot/dts/st/stm32f769-disco.dts +++ b/arch/arm/boot/dts/st/stm32f769-disco.dts @@ -128,10 +128,6 @@ vcc_3v3: vcc-3v3 { }; }; -&rcc { - compatible = "st,stm32f769-rcc", "st,stm32f746-rcc", "st,stm32-rcc"; -}; - &cec { pinctrl-0 = <&cec_pins_a>; pinctrl-names = "default"; @@ -140,11 +136,13 @@ &cec { &clk_hse { clock-frequency = <25000000>; + bootph-all; }; &dsi { #address-cells = <1>; #size-cells = <0>; + bootph-all; status = "okay"; ports { @@ -181,6 +179,50 @@ dsi_panel_in: endpoint { }; }; +&gpioa { + bootph-all; +}; + +&gpiob { + bootph-all; +}; + +&gpioc { + bootph-all; +}; + +&gpiod { + bootph-all; +}; + +&gpioe { + bootph-all; +}; + +&gpiof { + bootph-all; +}; + +&gpiog { + bootph-all; +}; + +&gpioh { + bootph-all; +}; + +&gpioi { + bootph-all; +}; + +&gpioj { + bootph-all; +}; + +&gpiok { + bootph-all; +}; + &i2c1 { pinctrl-0 = <&i2c1_pins_b>; pinctrl-names = "default"; @@ -190,6 +232,7 @@ &i2c1 { }; <dc { + bootph-all; status = "okay"; port { @@ -199,6 +242,19 @@ ltdc_out_dsi: endpoint { }; }; +&pinctrl { + bootph-all; +}; + +&pwrcfg { + bootph-all; +}; + +&rcc { + compatible = "st,stm32f769-rcc", "st,stm32f746-rcc", "st,stm32-rcc"; + bootph-all; +}; + &rtc { status = "okay"; }; @@ -219,6 +275,7 @@ &timers5 { /* Override timer5 to act as clockevent */ compatible = "st,stm32-timer"; interrupts = <50>; + bootph-all; status = "okay"; /delete-property/#address-cells; /delete-property/#size-cells; @@ -230,9 +287,20 @@ &timers5 { &usart1 { pinctrl-0 = <&usart1_pins_a>; pinctrl-names = "default"; + bootph-all; status = "okay"; }; +&usart1_pins_a { + bootph-all; + pins1 { + bootph-all; + }; + pins2 { + bootph-all; + }; +}; + &usbotg_hs { dr_mode = "otg"; phys = <&usbotg_hs_phy>; -- 2.43.0