From: Patrice Chotard <patrice.chotard@foss.st.com>
To: Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Maxime Coquelin <mcoquelin.stm32@gmail.com>,
Alexandre Torgue <alexandre.torgue@foss.st.com>,
Patrick Delaunay <patrick.delaunay@foss.st.com>,
Christoph Niedermaier <cniedermaier@dh-electronics.com>,
Marek Vasut <marex@denx.de>
Cc: <devicetree@vger.kernel.org>,
<linux-stm32@st-md-mailman.stormreply.com>,
<linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>, <kernel@dh-electronics.com>,
Patrice Chotard <patrice.chotard@foss.st.com>
Subject: [PATCH v7 3/7] ARM: dts: stm32: Add boot phase tags for STMicroelectronics h7 boards
Date: Tue, 26 May 2026 11:26:43 +0200 [thread overview]
Message-ID: <20260526-upstream_uboot_properties-v7-3-e17cd424d5db@foss.st.com> (raw)
In-Reply-To: <20260526-upstream_uboot_properties-v7-0-e17cd424d5db@foss.st.com>
The bootph-all flag was introduced in dt-schema
(dtschema/schemas/bootph.yaml) to define node usage across
different boot phases.
To ensure SD boot, timer, gpio, syscfg, clock and uart nodes need to be
present in all boot stages, so add missing bootph-all phase flag
to these nodes to support SD boot.
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
---
arch/arm/boot/dts/st/stm32h743i-disco.dts | 69 ++++++++++++++++++++++++++++++
arch/arm/boot/dts/st/stm32h743i-eval.dts | 69 ++++++++++++++++++++++++++++++
arch/arm/boot/dts/st/stm32h747i-disco.dts | 69 ++++++++++++++++++++++++++++++
arch/arm/boot/dts/st/stm32h750i-art-pi.dts | 69 ++++++++++++++++++++++++++++++
4 files changed, 276 insertions(+)
diff --git a/arch/arm/boot/dts/st/stm32h743i-disco.dts b/arch/arm/boot/dts/st/stm32h743i-disco.dts
index 78d55b77db7c..1b4b9bc5c72d 100644
--- a/arch/arm/boot/dts/st/stm32h743i-disco.dts
+++ b/arch/arm/boot/dts/st/stm32h743i-disco.dts
@@ -107,6 +107,59 @@ u-boot {
&clk_hse {
clock-frequency = <25000000>;
+ bootph-all;
+};
+
+&clk_lse {
+ bootph-all;
+};
+
+&clk_i2s {
+ bootph-all;
+};
+
+&gpioa {
+ bootph-all;
+};
+
+&gpiob {
+ bootph-all;
+};
+
+&gpioc {
+ bootph-all;
+};
+
+&gpiod {
+ bootph-all;
+};
+
+&gpioe {
+ bootph-all;
+};
+
+&gpiof {
+ bootph-all;
+};
+
+&gpiog {
+ bootph-all;
+};
+
+&gpioh {
+ bootph-all;
+};
+
+&gpioi {
+ bootph-all;
+};
+
+&gpioj {
+ bootph-all;
+};
+
+&gpiok {
+ bootph-all;
};
&mac {
@@ -126,6 +179,18 @@ phy0: ethernet-phy@0 {
};
};
+&pinctrl {
+ bootph-all;
+};
+
+&pwrcfg {
+ bootph-all;
+};
+
+&rcc {
+ bootph-all;
+};
+
&sdmmc1 {
pinctrl-names = "default", "opendrain", "sleep";
pinctrl-0 = <&sdmmc1_b4_pins_a>;
@@ -138,6 +203,10 @@ &sdmmc1 {
status = "okay";
};
+&timer5 {
+ bootph-all;
+};
+
&usart2 {
pinctrl-0 = <&usart2_pins_a>;
pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/st/stm32h743i-eval.dts b/arch/arm/boot/dts/st/stm32h743i-eval.dts
index e5e10b0758ee..55674fe05431 100644
--- a/arch/arm/boot/dts/st/stm32h743i-eval.dts
+++ b/arch/arm/boot/dts/st/stm32h743i-eval.dts
@@ -124,6 +124,59 @@ adc1: adc@0 {
&clk_hse {
clock-frequency = <25000000>;
+ bootph-all;
+};
+
+&clk_lse {
+ bootph-all;
+};
+
+&clk_i2s {
+ bootph-all;
+};
+
+&gpioa {
+ bootph-all;
+};
+
+&gpiob {
+ bootph-all;
+};
+
+&gpioc {
+ bootph-all;
+};
+
+&gpiod {
+ bootph-all;
+};
+
+&gpioe {
+ bootph-all;
+};
+
+&gpiof {
+ bootph-all;
+};
+
+&gpiog {
+ bootph-all;
+};
+
+&gpioh {
+ bootph-all;
+};
+
+&gpioi {
+ bootph-all;
+};
+
+&gpioj {
+ bootph-all;
+};
+
+&gpiok {
+ bootph-all;
};
&i2c1 {
@@ -155,6 +208,18 @@ phy0: ethernet-phy@0 {
};
};
+&pinctrl {
+ bootph-all;
+};
+
+&pwrcfg {
+ bootph-all;
+};
+
+&rcc {
+ bootph-all;
+};
+
&sdmmc1 {
pinctrl-names = "default", "opendrain", "sleep";
pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>;
@@ -169,6 +234,10 @@ &sdmmc1 {
status = "okay";
};
+&timer5 {
+ bootph-all;
+};
+
&usart1 {
pinctrl-0 = <&usart1_pins_a>;
pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/st/stm32h747i-disco.dts b/arch/arm/boot/dts/st/stm32h747i-disco.dts
index c9dcc680e26d..ef36454808d5 100644
--- a/arch/arm/boot/dts/st/stm32h747i-disco.dts
+++ b/arch/arm/boot/dts/st/stm32h747i-disco.dts
@@ -104,6 +104,59 @@ u-boot {
&clk_hse {
clock-frequency = <25000000>;
+ bootph-all;
+};
+
+&clk_lse {
+ bootph-all;
+};
+
+&clk_i2s {
+ bootph-all;
+};
+
+&gpioa {
+ bootph-all;
+};
+
+&gpiob {
+ bootph-all;
+};
+
+&gpioc {
+ bootph-all;
+};
+
+&gpiod {
+ bootph-all;
+};
+
+&gpioe {
+ bootph-all;
+};
+
+&gpiof {
+ bootph-all;
+};
+
+&gpiog {
+ bootph-all;
+};
+
+&gpioh {
+ bootph-all;
+};
+
+&gpioi {
+ bootph-all;
+};
+
+&gpioj {
+ bootph-all;
+};
+
+&gpiok {
+ bootph-all;
};
&mac {
@@ -123,6 +176,18 @@ phy0: ethernet-phy@0 {
};
};
+&pinctrl {
+ bootph-all;
+};
+
+&pwrcfg {
+ bootph-all;
+};
+
+&rcc {
+ bootph-all;
+};
+
&sdmmc1 {
pinctrl-names = "default", "opendrain", "sleep";
pinctrl-0 = <&sdmmc1_b4_pins_a>;
@@ -136,6 +201,10 @@ &sdmmc1 {
status = "okay";
};
+&timer5 {
+ bootph-all;
+};
+
&usart1 {
pinctrl-0 = <&usart1_pins_b>;
pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/st/stm32h750i-art-pi.dts b/arch/arm/boot/dts/st/stm32h750i-art-pi.dts
index 56c53e262da7..8dddc70c37a1 100644
--- a/arch/arm/boot/dts/st/stm32h750i-art-pi.dts
+++ b/arch/arm/boot/dts/st/stm32h750i-art-pi.dts
@@ -114,6 +114,15 @@ wlan_pwr: regulator-wlan {
&clk_hse {
clock-frequency = <25000000>;
+ bootph-all;
+};
+
+&clk_lse {
+ bootph-all;
+};
+
+&clk_i2s {
+ bootph-all;
};
&dma1 {
@@ -124,6 +133,50 @@ &dma2 {
status = "okay";
};
+&gpioa {
+ bootph-all;
+};
+
+&gpiob {
+ bootph-all;
+};
+
+&gpioc {
+ bootph-all;
+};
+
+&gpiod {
+ bootph-all;
+};
+
+&gpioe {
+ bootph-all;
+};
+
+&gpiof {
+ bootph-all;
+};
+
+&gpiog {
+ bootph-all;
+};
+
+&gpioh {
+ bootph-all;
+};
+
+&gpioi {
+ bootph-all;
+};
+
+&gpioj {
+ bootph-all;
+};
+
+&gpiok {
+ bootph-all;
+};
+
&mac {
status = "disabled";
pinctrl-0 = <ðernet_rmii>;
@@ -141,6 +194,18 @@ phy0: ethernet-phy@0 {
};
};
+&pinctrl {
+ bootph-all;
+};
+
+&pwrcfg {
+ bootph-all;
+};
+
+&rcc {
+ bootph-all;
+};
+
&sdmmc1 {
pinctrl-names = "default", "opendrain", "sleep";
pinctrl-0 = <&sdmmc1_b4_pins_a>;
@@ -196,6 +261,10 @@ partition@0 {
};
};
+&timer5 {
+ bootph-all;
+};
+
&usart2 {
pinctrl-0 = <&usart2_pins_a>;
pinctrl-names = "default";
--
2.43.0
next prev parent reply other threads:[~2026-05-26 9:27 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-26 9:26 [PATCH v7 0/7] Add boot phase tags for STMicroelectronics boards Patrice Chotard
2026-05-26 9:26 ` [PATCH v7 1/7] ARM: dts: stm32: Add boot phase tags for STMicroelectronics f4 boards Patrice Chotard
2026-05-26 9:26 ` [PATCH v7 2/7] ARM: dts: stm32: Add boot phase tags for STMicroelectronics f7 boards Patrice Chotard
2026-05-26 9:26 ` Patrice Chotard [this message]
2026-05-26 9:26 ` [PATCH v7 4/7] ARM: dts: stm32: Sort uart nodes by alphabetical order in stm32mp13xx-dhcor-som.dtsi Patrice Chotard
2026-05-26 9:26 ` [PATCH v7 5/7] ARM: dts: stm32: Add boot phase tags for STMicroelectronics mp13 boards Patrice Chotard
2026-05-26 9:26 ` [PATCH v7 6/7] ARM: dts: stm32: Add boot phase tags for STMicroelectronics mp15 boards Patrice Chotard
2026-05-26 9:26 ` [PATCH v7 7/7] arm64: dts: st: Add boot phase tags for STMicroelectronics mp2 boards Patrice Chotard
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