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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 2gW5lECWqsG9rdZiG+IMiNllSWmHYtqlHuizUcafqiSmQdvwmI+66daZccq+Y1r1wGYrQrzapVuhv/z/Zh7WyMm6twFHOLG6ArnFN7rOCJqMBfsmCBFF5tAK89P2jdrxPBgAYcTW7PQ3/vgVqJg8DGr1cudQ0YnvWkqKRHjzoMwbk5UVkKw/5v1OucoiezcUdyrHIXc182Ad4BlI1ZK9GZmA19eWYi/ive1rM78wtUnJvjresmNW4MWrau1ABI3Hfb578lc4VKj1j0O0gF6V8Kl3vU3pWIFWzlmTO+fDop09jI/1MUrVunj8dNbz7Kf2t/J0CpnBM6Z8dWfvx+HY42pCui57Bolrd/HTN0yAnsGrnIrbEK7I6kkyHLcKHJS+CRtc/S/kTYYdBlpnjjpd4tf6b2TFqM+iTOEGLLo/An+Zk6qpDWwx4MrMOuXZXm+p X-OriginatorOrg: foss.st.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 May 2026 09:26:48.5254 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bab0f95a-311d-4bc0-b522-08debb08e993 X-MS-Exchange-CrossTenant-Id: 75e027c9-20d5-47d5-b82f-77d7cd041e8f X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=75e027c9-20d5-47d5-b82f-77d7cd041e8f;Ip=[164.130.1.59];Helo=[smtpO365.st.com] X-MS-Exchange-CrossTenant-AuthSource: AM2PEPF0001C714.eurprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB9PR10MB7593 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260526_022701_400115_3CBDECE7 X-CRM114-Status: GOOD ( 12.62 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The bootph-all flag was introduced in dt-schema (dtschema/schemas/bootph.yaml) to define node usage across different boot phases. To ensure SD boot, timer, gpio, syscfg, clock and uart nodes need to be present in all boot stages, so add missing bootph-all phase flag to these nodes to support SD boot. Signed-off-by: Patrice Chotard --- arch/arm/boot/dts/st/stm32mp131.dtsi | 4 +- arch/arm/boot/dts/st/stm32mp135f-dhcor-dhsbc.dts | 21 +++++ arch/arm/boot/dts/st/stm32mp135f-dk.dts | 101 +++++++++++++++++++++++ arch/arm/boot/dts/st/stm32mp13xx-dhcor-som.dtsi | 101 +++++++++++++++++++++++ 4 files changed, 225 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/st/stm32mp131.dtsi b/arch/arm/boot/dts/st/stm32mp131.dtsi index 83ae59b73dd0..ec1e91101971 100644 --- a/arch/arm/boot/dts/st/stm32mp131.dtsi +++ b/arch/arm/boot/dts/st/stm32mp131.dtsi @@ -37,7 +37,7 @@ arm_wdt: watchdog { }; firmware { - optee { + optee: optee { method = "smc"; compatible = "linaro,optee-tz"; interrupt-parent = <&intc>; @@ -92,7 +92,7 @@ intc: interrupt-controller@a0021000 { <0xa0022000 0x2000>; }; - psci { + psci: psci { compatible = "arm,psci-1.0"; method = "smc"; }; diff --git a/arch/arm/boot/dts/st/stm32mp135f-dhcor-dhsbc.dts b/arch/arm/boot/dts/st/stm32mp135f-dhcor-dhsbc.dts index 70d85af46735..06b5b68e5f78 100644 --- a/arch/arm/boot/dts/st/stm32mp135f-dhcor-dhsbc.dts +++ b/arch/arm/boot/dts/st/stm32mp135f-dhcor-dhsbc.dts @@ -354,6 +354,21 @@ timer@12 { }; }; +&uart4 { + bootph-all; +}; + +&uart4_pins_b { + bootph-all; + + pins1 { + bootph-all; + }; + pins2 { + bootph-all; + }; +}; + &usart1 { /* Expansion connector: RX:pin33 TX:pin37 */ pinctrl-names = "default", "sleep", "idle"; pinctrl-0 = <&usart1_pins_b>; @@ -371,6 +386,10 @@ &usart2 { /* Expansion connector: RX:pin10 TX:pin8 RTS:pin11 CTS:pin36 */ status = "okay"; }; +&usbphyc { + bootph-all; +}; + &usbh_ehci { phys = <&usbphyc_port0>; status = "okay"; @@ -436,6 +455,7 @@ connector { /* LDO2 is expansion connector 3V3 supply on STM32MP13xx DHCOR DHSBC rev.200 */ &vdd_ldo2 { + bootph-all; regulator-always-on; regulator-boot-on; regulator-min-microvolt = <3300000>; @@ -444,6 +464,7 @@ &vdd_ldo2 { /* LDO5 is carrier board 3V3 supply on STM32MP13xx DHCOR DHSBC rev.200 */ &vdd_sd { + bootph-all; regulator-always-on; regulator-boot-on; regulator-min-microvolt = <3300000>; diff --git a/arch/arm/boot/dts/st/stm32mp135f-dk.dts b/arch/arm/boot/dts/st/stm32mp135f-dk.dts index 6022e73f58af..43b8a7eed01b 100644 --- a/arch/arm/boot/dts/st/stm32mp135f-dk.dts +++ b/arch/arm/boot/dts/st/stm32mp135f-dk.dts @@ -182,6 +182,10 @@ &arm_wdt { status = "okay"; }; +&bsec { + bootph-all; +}; + &crc1 { status = "okay"; }; @@ -253,6 +257,42 @@ phy0_eth1: ethernet-phy@0 { }; }; +&gpioa { + bootph-all; +}; + +&gpiob { + bootph-all; +}; + +&gpioc { + bootph-all; +}; + +&gpiod { + bootph-all; +}; + +&gpioe { + bootph-all; +}; + +&gpiof { + bootph-all; +}; + +&gpiog { + bootph-all; +}; + +&gpioh { + bootph-all; +}; + +&gpioi { + bootph-all; +}; + &i2c1 { pinctrl-names = "default", "sleep"; /* SDA on PE8 = CN8.27, SCL on PD12 = CN8.28 */ @@ -388,6 +428,7 @@ goodix: goodix-ts@5d { &iwdg2 { timeout-sec = <32>; + bootph-all; status = "okay"; }; @@ -395,6 +436,7 @@ <dc { pinctrl-names = "default", "sleep"; pinctrl-0 = <<dc_pins_a>; pinctrl-1 = <<dc_sleep_pins_a>; + bootph-some-ram; status = "okay"; port { @@ -404,6 +446,22 @@ ltdc_out_rgb: endpoint { }; }; +&optee { + bootph-all; +}; + +&pinctrl { + bootph-all; +}; + +&psci { + bootph-some-ram; +}; + +&rcc { + bootph-all; +}; + &rtc { pinctrl-names = "default"; pinctrl-0 = <&rtc_rsvd_pins_a>; @@ -415,6 +473,14 @@ rtc_lsco_pins_a: rtc-lsco-0 { }; }; +&scmi { + bootph-all; +}; + +&scmi_clk { + bootph-all; +}; + &scmi_regu { scmi_vdd_adc: regulator@10 { reg = ; @@ -438,6 +504,10 @@ scmi_v3v3_sw: regulator@19 { }; }; +&scmi_reset { + bootph-all; +}; + &sdmmc1 { pinctrl-names = "default", "opendrain", "sleep"; pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_clk_pins_a>; @@ -448,9 +518,24 @@ &sdmmc1 { st,neg-edge; bus-width = <4>; vmmc-supply = <&scmi_vdd_sd>; + bootph-pre-ram; status = "okay"; }; +&sdmmc1_b4_pins_a { + bootph-pre-ram; + pins { + bootph-pre-ram; + }; +}; + +&sdmmc1_clk_pins_a { + bootph-pre-ram; + pins { + bootph-pre-ram; + }; +}; + /* Wifi */ &sdmmc2 { pinctrl-names = "default", "opendrain", "sleep"; @@ -482,6 +567,10 @@ &spi5 { status = "disabled"; }; +&syscfg { + bootph-all; +}; + &timers3 { /delete-property/dmas; /delete-property/dma-names; @@ -575,9 +664,20 @@ &uart4 { pinctrl-2 = <&uart4_idle_pins_a>; /delete-property/dmas; /delete-property/dma-names; + bootph-all; status = "okay"; }; +&uart4_pins_a { + bootph-all; + pins1 { + bootph-all; + }; + pins2 { + bootph-all; + }; +}; + &uart8 { pinctrl-names = "default", "sleep", "idle"; /* TX on PE1 = CN8.37, RX on PF9 = CN8.33 */ @@ -645,6 +745,7 @@ usbotg_hs_ep: endpoint { }; &usbphyc { + bootph-all; status = "okay"; }; diff --git a/arch/arm/boot/dts/st/stm32mp13xx-dhcor-som.dtsi b/arch/arm/boot/dts/st/stm32mp13xx-dhcor-som.dtsi index 54ece71085c1..4efaca84a72c 100644 --- a/arch/arm/boot/dts/st/stm32mp13xx-dhcor-som.dtsi +++ b/arch/arm/boot/dts/st/stm32mp13xx-dhcor-som.dtsi @@ -54,6 +54,46 @@ vin: vin { }; }; +&bsec { + bootph-all; +}; + +&gpioa { + bootph-all; +}; + +&gpiob { + bootph-all; +}; + +&gpioc { + bootph-all; +}; + +&gpiod { + bootph-all; +}; + +&gpioe { + bootph-all; +}; + +&gpiof { + bootph-all; +}; + +&gpiog { + bootph-all; +}; + +&gpioh { + bootph-all; +}; + +&gpioi { + bootph-all; +}; + &i2c3 { i2c-scl-rising-time-ns = <96>; i2c-scl-falling-time-ns = <3>; @@ -216,9 +256,18 @@ eeprom0wl: eeprom@58 { &iwdg2 { timeout-sec = <32>; + bootph-all; status = "okay"; }; +&pinctrl { + bootph-all; +}; + +&psci { + bootph-some-ram; +}; + &qspi { pinctrl-names = "default", "sleep"; pinctrl-0 = <&qspi_clk_pins_a @@ -229,6 +278,7 @@ &qspi_bk1_sleep_pins_a &qspi_cs1_sleep_pins_a>; #address-cells = <1>; #size-cells = <0>; + bootph-all; status = "okay"; flash0: flash@0 { @@ -238,9 +288,35 @@ flash0: flash@0 { spi-max-frequency = <108000000>; #address-cells = <1>; #size-cells = <1>; + bootph-all; }; }; +&qspi_clk_pins_a { + bootph-all; + pins { + bootph-all; + }; +}; + +&qspi_bk1_pins_a { + bootph-all; + pins { + bootph-all; + }; +}; + +&qspi_cs1_pins_a { + bootph-all; + pins { + bootph-all; + }; +}; + +&rcc { + bootph-all; +}; + /* SDIO WiFi */ &sdmmc1 { pinctrl-names = "default", "opendrain", "sleep"; @@ -285,6 +361,10 @@ &sdmmc2 { status = "okay"; }; +&syscfg { + bootph-all; +}; + /* Console UART */ &uart4 { pinctrl-names = "default", "sleep", "idle"; @@ -312,3 +392,24 @@ bluetooth { shutdown-gpios = <&gpioi 2 GPIO_ACTIVE_HIGH>; }; }; + +&vdd { + bootph-all; +}; + +&vddcpu { + bootph-all; +}; + + +&vddcore { + bootph-all; +}; + +&vdd_ddr { + bootph-all; +}; + +&vref_ddr { + bootph-all; +}; -- 2.43.0