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Thu, 28 May 2026 03:16:32 -0700 From: Ashish Mhetre To: , , , , CC: , , , , Ashish Mhetre Subject: [PATCH 2/2] iommu/arm-smmu-v3: Issue CFGI/TLBI twice on Tegra264 Date: Thu, 28 May 2026 10:16:17 +0000 Message-ID: <20260528101617.4068249-3-amhetre@nvidia.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20260528101617.4068249-1-amhetre@nvidia.com> References: <20260528101617.4068249-1-amhetre@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MWH0EPF000A672E:EE_|SA3PR12MB9227:EE_ X-MS-Office365-Filtering-Correlation-Id: f277ebb5-8c21-4882-9fa8-08debca237cc X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700016|82310400026|376014|18002099003|22082099003|3023799007|56012099006|11063799006; X-Microsoft-Antispam-Message-Info: JGyA0AosYjNNi/YZNJ7eTTwjU7PnbT/oFvM2hyf4qTwZFVNlUShWBxr0Hgef+gRJNhTEfhFzY7kdV/y1jAPTWTg1dEpYivtMUwHPB66DHTfow9CWzIVQOtZr9A1/Ky9smCgA/XDQtLZ43FSEq8l+hM3im34hUSZwxALaIsvNfsMlRJoHJnVoJzJP+URDE9umIZ5tU12y3PkNTDzx3v7U899vlFZXAm75QKMKZY2pnKWQt8Pg+z0SMD0jd9+ZQlQXs5PsaPXLviUsbm0Avjqocyhe4NJ/L0BYqJSEIDN1CR7qUX7cuqV+VuQViEClIuE4e0mckH6Dzjf+XLcB5yP3GKIG6r4YeOGuNceDCJ7XTF27OChVeJSNaglS/tUlRIUomBzXxLI030Y8zpBUoxVcFCrUA7qMpvECLeMgC2sOhASgZQMux0Xgyvsfh+OFGKe7nFbSHQjvha+x91GzxZ3lUm2C52IrIO54qE4HSmi696CBfco2LuZieOpPIBlRiPBt5vm5wnX0TebPfsoSJrIYw+Ncur8FJTy9zLoTxRYQxOQ+jokraxXOx/s1OhWof36k9muHd3A1yZ/imlwySHFIlFheNXp0qNFys+9MB1UXBhhzZZNztflqBXlFpirYmjcpm52ZjOTMDt7l4/fj01yRH0D7BUXQlx1LbxPEMWlQBJWeaCQo6IquBQ7yuSzMh5NXp/uv4vVEFRQz0BhUvntPIFChkZ3Tq5o9BjsZkqNoxhI= X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(36860700016)(82310400026)(376014)(18002099003)(22082099003)(3023799007)(56012099006)(11063799006);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: jHe7ffkAkyrFvurxF4lHiVl1BlrBgv23PTxPOijLDecC5VXVhWQSR1+0Ci703tNVDdP8gQ1yjuNWtdFaJ2QnOJjl9kR3nIg0Tsp01I8PCzJJEFjuXObUdrYbUouPyV4atKPPu3VAQXyBE115YO/EjH0e/3vykf0ISAd/5E+wgXiv4sizHZZ8zvmnqlDFgRCsKCfjsgicCmK/IaiCsj6brahBs9LmKugla3x4s3yPF0SKOdBFJRa779zONogPTJx+oYLScgo/naEGZylBGCql+ZaWn/ZEKF5t1ipcm41ZDl1zrPiX3DCwBuvv5FieVLDNa4Uf/Kx8EOKbZNOKgUypFPoTOoqCA3UzcbBXdkzPVB3cFzSAn4fasnwl8mIqB/vDKXy0Qg5ojuDNnQ1hwrfHsvqLpoQKtyqjTMG2HSltzyMD+c0hdoCOdF+dsauZdjpV X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 May 2026 10:16:43.9083 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f277ebb5-8c21-4882-9fa8-08debca237cc X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000A672E.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA3PR12MB9227 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260528_031653_490270_49CB0638 X-CRM114-Status: GOOD ( 16.43 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Apply the workaround for Tegra264 erratum by issuing every CFGI/TLBI command twice on affected SMMU instances, with CMD_SYNC after each. The erratum requires this exact sequencing: TLBI/CFGI ... CMD_SYNC TLBI/CFGI ... CMD_SYNC To get this sequence with minimal surgery, hook the workaround into arm_smmu_cmdq_issue_cmdlist(). Rename the original function to __arm_smmu_cmdq_issue_cmdlist() and add a thin wrapper that, on affected SMMUs and when @sync is true, re-issues the same cmdlist a second time. A new arm_smmu_cmd_needs_tlbi_twice() helper classifies which opcodes need the doubling: CFGI_* and TLBI_*. For batches that exceed CMDQ_BATCH_ENTRIES commands, arm_smmu_cmdq_batch_add_cmd_p() normally flushes the full buffer with sync=false, deferring the SYNC to the eventual batch_submit(). On affected SMMUs this would leave the first chunk's commands issued only once, since the WAR hook in arm_smmu_cmdq_issue_cmdlist() only fires on synced submissions. Force a SYNC on the capacity rollover when the buffer carries CFGI/TLBI commands so every flushed chunk is correctly doubled. Signed-off-by: Ashish Mhetre --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 66 +++++++++++++++++++-- 1 file changed, 61 insertions(+), 5 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index 88296c0a5337..38d45f175a2c 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -698,10 +698,10 @@ static void arm_smmu_cmdq_write_entries(struct arm_smmu_cmdq *cmdq, * insert their own list of commands then all of the commands from one * CPU will appear before any of the commands from the other CPU. */ -int arm_smmu_cmdq_issue_cmdlist(struct arm_smmu_device *smmu, - struct arm_smmu_cmdq *cmdq, - struct arm_smmu_cmd *cmds, int n, - bool sync) +static int __arm_smmu_cmdq_issue_cmdlist(struct arm_smmu_device *smmu, + struct arm_smmu_cmdq *cmdq, + struct arm_smmu_cmd *cmds, int n, + bool sync) { struct arm_smmu_cmd cmd_sync; u32 prod; @@ -820,6 +820,52 @@ int arm_smmu_cmdq_issue_cmdlist(struct arm_smmu_device *smmu, return ret; } +/* + * Returns true if @opcode is a CFGI_* or TLBI_* command, i.e. one of the + * invalidations covered by Tegra264 erratum (see ARM_SMMU_OPT_TLBI_TWICE). + */ +static bool arm_smmu_cmd_needs_tlbi_twice(u8 opcode) +{ + switch (opcode) { + case CMDQ_OP_CFGI_STE: + case CMDQ_OP_CFGI_ALL: + case CMDQ_OP_CFGI_CD: + case CMDQ_OP_CFGI_CD_ALL: + case CMDQ_OP_TLBI_NH_ALL: + case CMDQ_OP_TLBI_NH_ASID: + case CMDQ_OP_TLBI_NH_VA: + case CMDQ_OP_TLBI_NH_VAA: + case CMDQ_OP_TLBI_EL2_ALL: + case CMDQ_OP_TLBI_EL2_ASID: + case CMDQ_OP_TLBI_EL2_VA: + case CMDQ_OP_TLBI_S12_VMALL: + case CMDQ_OP_TLBI_S2_IPA: + case CMDQ_OP_TLBI_NSNH_ALL: + return true; + default: + return false; + } +} + +int arm_smmu_cmdq_issue_cmdlist(struct arm_smmu_device *smmu, + struct arm_smmu_cmdq *cmdq, + struct arm_smmu_cmd *cmds, int n, + bool sync) +{ + int ret = __arm_smmu_cmdq_issue_cmdlist(smmu, cmdq, cmds, n, sync); + + /* + * The driver's batch invariants keep a single submission's + * opcode class uniform, so checking the first command is enough. + */ + if (!ret && sync && (smmu->options & ARM_SMMU_OPT_TLBI_TWICE) && + arm_smmu_cmd_needs_tlbi_twice(FIELD_GET(CMDQ_0_OP, + cmds[0].data[0]))) + ret = __arm_smmu_cmdq_issue_cmdlist(smmu, cmdq, cmds, n, sync); + + return ret; +} + static int arm_smmu_cmdq_issue_cmd_p(struct arm_smmu_device *smmu, struct arm_smmu_cmd *cmd, bool sync) { @@ -863,8 +909,18 @@ static void arm_smmu_cmdq_batch_add_cmd_p(struct arm_smmu_device *smmu, } if (cmds->num == CMDQ_BATCH_ENTRIES) { + /* + * Force a SYNC only when the batch carries commands that + * have to be doubled (see ARM_SMMU_OPT_TLBI_TWICE). + * The batch holds a uniform opcode class, so checking + * the first command is sufficient. + */ + bool need_sync = (smmu->options & ARM_SMMU_OPT_TLBI_TWICE) && + arm_smmu_cmd_needs_tlbi_twice(FIELD_GET(CMDQ_0_OP, + cmds->cmds[0].data[0])); + arm_smmu_cmdq_issue_cmdlist(smmu, cmds->cmdq, cmds->cmds, - cmds->num, false); + cmds->num, need_sync); arm_smmu_cmdq_batch_init_cmd(smmu, cmds, cmd); } -- 2.50.1