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Fri, 29 May 2026 15:56:08 +0000 (GMT) Received: from tuxmaker.boeblingen.de.ibm.com (unknown [9.87.85.9]) by smtpav07.fra02v.mail.ibm.com (Postfix) with ESMTP; Fri, 29 May 2026 15:56:08 +0000 (GMT) From: Steffen Eiden To: kvm@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-s390@vger.kernel.org Cc: Alexander Gordeev , Andreas Grapentin , Arnd Bergmann , Catalin Marinas , Christian Borntraeger , Claudio Imbrenda , David Hildenbrand , Friedrich Welter , Gautam Gala , Hariharan Mari , Heiko Carstens , Hendrik Brueckner , Ilya Leoshkevich , Janosch Frank , Joey Gouly , Marc Zyngier , Nico Boehr , Nina Schoetterl-Glausch , Oliver Upton , Paolo Bonzini , Suzuki K Poulose , Sven Schnelle , Ulrich Weigand , Vasily Gorbik , Will Deacon , Zenghui Yu Subject: [PATCH v1 18/26] arm64: Extract cache definitions Date: Fri, 29 May 2026 17:55:51 +0200 Message-ID: <20260529155601.2927240-19-seiden@linux.ibm.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260529155601.2927240-1-seiden@linux.ibm.com> References: <20260529155601.2927240-1-seiden@linux.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-TM-AS-GCONF: 00 X-Authority-Analysis: v=2.4 cv=L4MtheT8 c=1 sm=1 tr=0 ts=6a19b721 cx=c_pps a=bLidbwmWQ0KltjZqbj+ezA==:117 a=bLidbwmWQ0KltjZqbj+ezA==:17 a=NGcC8JguVDcA:10 a=VkNPw1HP01LnGYTKEx00:22 a=RnoormkPH1_aCDwRdu11:22 a=iQ6ETzBq9ecOQQE5vZCe:22 a=VnNF1IyMAAAA:8 a=pRZW_VWv9im2awHLU-wA:9 X-Proofpoint-ORIG-GUID: slVjF5f-oq9tzH_qacJlnFctQDu0_ACn X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTI5MDE1NiBTYWx0ZWRfX8oPtDgaMF3m/ MK1rxSS24KimAM7XsXvGSzWrJUIQDlWN7vlqTJKBpq4YLq8slBqI21QltNLBxqL6sfhAYWDMkmn jX/TbdHyjz1bfKFB6mWCYOCXysOCkf0GM+kfz9F1UvX6lZPWlP0kesce3iV3o9EA5dZ2ICfO9PF lmHWj9khK3BOvHHKKJrens/l+KFqet1gMMLO0NKL9pnbMKOix2jizeCl48YESDv/pHUhCw/+C6L dq++JTdd8ckUxpzBagTClP5VP/LHq+0RMIOhsvyiWr4u6RU2v+9aqEqgewnrpXvI/NFyN3uI8r1 TNBGtV1n63cM5DGg0XHURVH9I1jma47Yz3PNyuk7Xu8xSp2Au66orrd9iYGPMwIL1WKM1ONyU3/ h/nmLRaakTdUQNPh63BJBCUD0n342it//rYPKiJaAaia1dEfoy/EVQkP7Ereh3zkaVxf28ToZgQ gFynb9FophKzvpV/E3w== X-Proofpoint-GUID: slVjF5f-oq9tzH_qacJlnFctQDu0_ACn X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-05-29_04,2026-05-28_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 lowpriorityscore=0 suspectscore=0 clxscore=1015 malwarescore=0 bulkscore=0 impostorscore=0 adultscore=0 priorityscore=1501 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605210000 definitions=main-2605290156 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260529_085627_898170_DA3C7ECA X-CRM114-Status: GOOD ( 15.40 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Move CPU type definitions from arch/arm64/include/asm/cache.h.h to include/arch/arm64/asm/cache-defs.h to prepare sharing with other architectures. No functional changes. Signed-off-by: Steffen Eiden --- arch/arm64/include/asm/cache.h | 19 ++----------------- include/arch/arm64/asm/cache-defs.h | 22 ++++++++++++++++++++++ 2 files changed, 24 insertions(+), 17 deletions(-) create mode 100644 include/arch/arm64/asm/cache-defs.h diff --git a/arch/arm64/include/asm/cache.h b/arch/arm64/include/asm/cache.h index 10a7ffadee3d..0f67fe470c29 100644 --- a/arch/arm64/include/asm/cache.h +++ b/arch/arm64/include/asm/cache.h @@ -5,26 +5,11 @@ #ifndef __ASM_CACHE_H #define __ASM_CACHE_H +#include + #define L1_CACHE_SHIFT (6) #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) -#define CLIDR_LOUU_SHIFT 27 -#define CLIDR_LOC_SHIFT 24 -#define CLIDR_LOUIS_SHIFT 21 - -#define CLIDR_LOUU(clidr) (((clidr) >> CLIDR_LOUU_SHIFT) & 0x7) -#define CLIDR_LOC(clidr) (((clidr) >> CLIDR_LOC_SHIFT) & 0x7) -#define CLIDR_LOUIS(clidr) (((clidr) >> CLIDR_LOUIS_SHIFT) & 0x7) - -/* Ctypen, bits[3(n - 1) + 2 : 3(n - 1)], for n = 1 to 7 */ -#define CLIDR_CTYPE_SHIFT(level) (3 * (level - 1)) -#define CLIDR_CTYPE_MASK(level) (7 << CLIDR_CTYPE_SHIFT(level)) -#define CLIDR_CTYPE(clidr, level) \ - (((clidr) & CLIDR_CTYPE_MASK(level)) >> CLIDR_CTYPE_SHIFT(level)) - -/* Ttypen, bits [2(n - 1) + 34 : 2(n - 1) + 33], for n = 1 to 7 */ -#define CLIDR_TTYPE_SHIFT(level) (2 * ((level) - 1) + CLIDR_EL1_Ttypen_SHIFT) - /* * Memory returned by kmalloc() may be used for DMA, so we must make * sure that all such allocations are cache aligned. Otherwise, diff --git a/include/arch/arm64/asm/cache-defs.h b/include/arch/arm64/asm/cache-defs.h new file mode 100644 index 000000000000..bb0ab69a9cd6 --- /dev/null +++ b/include/arch/arm64/asm/cache-defs.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef __ASM_CACHE_DEFS_H +#define __ASM_CACHE_DEFS_H + +#define CLIDR_LOUU_SHIFT 27 +#define CLIDR_LOC_SHIFT 24 +#define CLIDR_LOUIS_SHIFT 21 + +#define CLIDR_LOUU(clidr) (((clidr) >> CLIDR_LOUU_SHIFT) & 0x7) +#define CLIDR_LOC(clidr) (((clidr) >> CLIDR_LOC_SHIFT) & 0x7) +#define CLIDR_LOUIS(clidr) (((clidr) >> CLIDR_LOUIS_SHIFT) & 0x7) + +/* Ctypen, bits[3(n - 1) + 2 : 3(n - 1)], for n = 1 to 7 */ +#define CLIDR_CTYPE_SHIFT(level) (3 * (level - 1)) +#define CLIDR_CTYPE_MASK(level) (7 << CLIDR_CTYPE_SHIFT(level)) +#define CLIDR_CTYPE(clidr, level) \ + (((clidr) & CLIDR_CTYPE_MASK(level)) >> CLIDR_CTYPE_SHIFT(level)) + +/* Ttypen, bits [2(n - 1) + 34 : 2(n - 1) + 33], for n = 1 to 7 */ +#define CLIDR_TTYPE_SHIFT(level) (2 * ((level) - 1) + CLIDR_EL1_Ttypen_SHIFT) + +#endif /* __ASM_CACHE_DEFS_H */ -- 2.53.0