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Mon, 1 Jun 2026 03:48:50 -0700 Received: from drhqmail202.nvidia.com (10.126.190.181) by drhqmail202.nvidia.com (10.126.190.181) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Mon, 1 Jun 2026 03:48:49 -0700 Received: from build-amhetre-focal-20250829.internal (10.127.8.12) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server id 15.2.2562.20 via Frontend Transport; Mon, 1 Jun 2026 03:48:49 -0700 From: Ashish Mhetre To: , , , , CC: , , , , Ashish Mhetre Subject: [PATCH v3 2/3] iommu/arm-smmu-v3: Detect Tegra264 erratum Date: Mon, 1 Jun 2026 10:48:44 +0000 Message-ID: <20260601104845.995005-3-amhetre@nvidia.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20260601104845.995005-1-amhetre@nvidia.com> References: <20260601104845.995005-1-amhetre@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF000023D4:EE_|BY5PR12MB4324:EE_ X-MS-Office365-Filtering-Correlation-Id: efd1d449-a5ec-4fd6-4aca-08debfcb64cc X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|82310400026|376014|1800799024|18002099003|22082099003|56012099006|11063799006|3023799007; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: dDkENlnqyqsA3ivoo84kMNVKPkd4LJkkd2M3AntraZG+C1YAna95mIyif9I3qCGlwV1dQ3z8LpKNw+/rQxgUMeIJypSnqPoo9mfuF//LMgJDMr+zk2DxmKFlXE4qaMfesUFj+gHN1GlpRlXHjt/IVdrhTR/zml6vn/piHeBOeKpHdgW3yg2ah+eicvFGfMdMpCTVGzueQPuQJRByZQbA8Anw16lJhucJ+VZ0T+02WugqE/Or3zFbwNnGYqbuwAkEbFSUxK7vSLIO0c8kumovGjf2X2vjtyKN3ra0BweoksO3cbzMKicBdotGWyU7cz/VP+OmZCAGKy5dc189LIEN3XBLZCMS2WXRBXl/vVfk931a6M7oVytasJ8A3cacHK7UZy6wSEZiGmZ5BnaV7CrlOLtduqRLUR0QoZtTjvKBRtasv4Swo7oXO9lttr3PrQgh X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Jun 2026 10:49:02.3349 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: efd1d449-a5ec-4fd6-4aca-08debfcb64cc X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF000023D4.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4324 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260601_114909_729316_5BA408A2 X-CRM114-Status: GOOD ( 15.21 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Tegra264 SMMU is affected by erratum where a TLB entry can survive an invalidation that races with concurrent traffic targeting the same entry. The hardware-recommended software workaround is to issue every CFGI/TLBI command (each followed by CMD_SYNC) twice. The second issue is guaranteed to evict the entry. ATC_INV is not affected and must not be doubled. The erratum is not flagged by any SMMUv3 IDR/IIDR register, so it cannot be detected from hardware ID. Tegra264 boots from device tree only and has no ACPI/IORT support, so detection is through device tree only. Add the ARM_SMMU_OPT_TLBI_TWICE option and set it on instances matching the existing "nvidia,tegra264-smmu" compatible. Also add a static-inline arm_smmu_cmd_needs_tlbi_twice() classifier in arm-smmu-v3.h so that subsequent changes wiring the workaround into the CMDQ submission and iommufd batching paths can share a single predicate. No callers consume the option yet; a subsequent change will wire the workaround into the CMDQ issue paths. Signed-off-by: Ashish Mhetre Reviewed-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 4 ++- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 40 +++++++++++++++++++++ 2 files changed, 43 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index 4d29bd343460..08684bd40a6d 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -5243,8 +5243,10 @@ static int arm_smmu_device_dt_probe(struct platform_device *pdev, if (of_dma_is_coherent(dev->of_node)) smmu->features |= ARM_SMMU_FEAT_COHERENCY; - if (of_device_is_compatible(dev->of_node, "nvidia,tegra264-smmu")) + if (of_device_is_compatible(dev->of_node, "nvidia,tegra264-smmu")) { tegra_cmdqv_dt_probe(dev->of_node, smmu); + smmu->options |= ARM_SMMU_OPT_TLBI_TWICE; + } return ret; } diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h index 16353596e08a..106034c348a1 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -928,6 +928,14 @@ struct arm_smmu_device { #define ARM_SMMU_OPT_MSIPOLL (1 << 2) #define ARM_SMMU_OPT_CMDQ_FORCE_SYNC (1 << 3) #define ARM_SMMU_OPT_TEGRA241_CMDQV (1 << 4) +/* + * Tegra264 erratum: a TLB entry can survive an invalidation that races + * with concurrent traffic targeting the same entry. The software + * workaround is to issue every CFGI/TLBI command twice, each followed + * by CMD_SYNC. The second issue is guaranteed to evict the entry. + * ATC_INV commands are not affected and must not be doubled. + */ +#define ARM_SMMU_OPT_TLBI_TWICE (1 << 5) u32 options; struct arm_smmu_cmdq cmdq; @@ -1211,6 +1219,38 @@ int arm_smmu_cmdq_issue_cmdlist(struct arm_smmu_device *smmu, struct arm_smmu_cmd *cmds, int n, bool sync); +/* + * Returns true if @cmd is one of the CFGI_* or TLBI_* commands covered + * by the Tegra264 erratum (see ARM_SMMU_OPT_TLBI_TWICE) on an affected + * SMMU instance. + */ +static inline bool arm_smmu_cmd_needs_tlbi_twice(struct arm_smmu_device *smmu, + struct arm_smmu_cmd *cmd) +{ + if (!(smmu->options & ARM_SMMU_OPT_TLBI_TWICE)) + return false; + + switch (FIELD_GET(CMDQ_0_OP, cmd->data[0])) { + case CMDQ_OP_CFGI_STE: + case CMDQ_OP_CFGI_ALL: + case CMDQ_OP_CFGI_CD: + case CMDQ_OP_CFGI_CD_ALL: + case CMDQ_OP_TLBI_NH_ALL: + case CMDQ_OP_TLBI_NH_ASID: + case CMDQ_OP_TLBI_NH_VA: + case CMDQ_OP_TLBI_NH_VAA: + case CMDQ_OP_TLBI_EL2_ALL: + case CMDQ_OP_TLBI_EL2_ASID: + case CMDQ_OP_TLBI_EL2_VA: + case CMDQ_OP_TLBI_S12_VMALL: + case CMDQ_OP_TLBI_S2_IPA: + case CMDQ_OP_TLBI_NSNH_ALL: + return true; + default: + return false; + } +} + #ifdef CONFIG_ARM_SMMU_V3_SVA bool arm_smmu_sva_supported(struct arm_smmu_device *smmu); void arm_smmu_sva_notifier_synchronize(void); -- 2.50.1