From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 670D4CD6E4A for ; Wed, 3 Jun 2026 03:36:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:MIME-Version:Content-Type: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=SZJVak88/aC7UTVK2wwbeD1rPLF/qNGzBGGJ5rAWfSg=; b=iI48wclwzpLB4zpOvMhirpK0/J BTC/AeO2P2j29/HMMmMrf+/xGL6LHJBoW0PBaOy+vdMc+Uns88Iogr0NAypU0RmYasr9qm7uIpoDi a3sFM/u0RY5mD0Y14kpEWZuJjDXQ46SRt4iv8uexUn/Dd2yEK+pKUPpaokUvtAxG9Jl5fsrdIQyVc M2VLUckZQ7+78ERQYyeuqv1Xt6V/oOm6WgW0n0s5CUWN2iBwTtCCZ+rttkFHBzSbzfHOBQ6vNleU+ x4L6ihyOFH6TVryHyB9vWnJwPNoRNx4FzEMUs6WC+qD/5iaQbVVu6rV3K2u83bdUvffhHCbGiFrNY QORanfUw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.99.1 #2 (Red Hat Linux)) id 1wUcPP-0000000EBvr-1ddP; Wed, 03 Jun 2026 03:36:47 +0000 Received: from smtpbgeu2.qq.com ([18.194.254.142]) by bombadil.infradead.org with esmtps (Exim 4.99.1 #2 (Red Hat Linux)) id 1wUcPI-0000000EBrR-2QJl; Wed, 03 Jun 2026 03:36:45 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=airkyi.com; s=altu2504; t=1780457747; bh=SZJVak88/aC7UTVK2wwbeD1rPLF/qNGzBGGJ5rAWfSg=; h=From:To:Subject:Date:Message-Id; b=mxWcYVI620l/6x+AdUfkE00+luazpSOUF8CzhhSvSpoglnYq3cO/9aogVbe2Suy5n cPqptjNBS5tEY8CSvb7N+CB4IFDYLY3Kjy09HskYownsqS7qa+PK8UJniHqDQFowTl poMn0S+JMFfV2QRd8nITuzMoGbfLUww6WrBThQX8= X-QQ-mid: zesmtpsz3t1780457744t40a9fe0e X-QQ-Originating-IP: PQ/u+gWD46vcVDfQQRGeC38c+LI/83M6xwchE1O5Lik= Received: from DESKTOP-8BT1A2O.localdomain ( [58.22.7.114]) by bizesmtp.qq.com (ESMTP) with id ; Wed, 03 Jun 2026 11:35:41 +0800 (CST) X-QQ-SSF: 0000000000000000000000000000000 X-QQ-GoodBg: 0 X-BIZMAIL-ID: 6389778551223950337 From: Chaoyi Chen To: Sandy Huang , =?UTF-8?q?Heiko=20St=C3=BCbner?= , Andy Yan , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Guochun Huang Cc: dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Chaoyi Chen Subject: [PATCH v2 1/3] drm/rockchip: dsi: Add maximum per lane bit rate calculation Date: Wed, 3 Jun 2026 11:35:30 +0800 Message-Id: <20260603033532.164-2-kernel@airkyi.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20260603033532.164-1-kernel@airkyi.com> References: <20260603033532.164-1-kernel@airkyi.com> X-QQ-SENDSIZE: 520 Feedback-ID: zesmtpsz:airkyi.com:qybglogicsvrgz:qybglogicsvrgz6b-0 X-QQ-XMAILINFO: MCg5+ArSTX6cI8MT6PFu0yKBnZg7NNmzMhqB5fcT0Ih+hPtX+3PAoGHn Uh2QfOyjF8VCqpCni/HY8bt0EzY4wNu3HxXF71jPkEvz9BzMmAnIoNw2iE+G/JhH9BbvHRI fxl2mXWyGEDguCVrwBT0rv7t3IeBdfQ8/caQdYice7EkurIh7Zc+Wu1sGvimuIxOXu5WY3D cZyiBqWulXnxjz2DC5lY5bAU6Z7FHloUWLkJZNubtxiK3MYCOScPboSwiUcLOppt5EVcgBY NeY6+t7m/wTkqbTlUbLmVX9YUjBvgEmY0Ou81CvhmA0W8niIlfkizyEAGKYFeCNtd8C4KpZ 78oUewjiRH/jR6nXnOpHJijFquyJqYgNooqxaSwlZxHInncqUT8sq67voPnJmIalL2fszpv je9U595Z+DHhRiPU+b+SVZqyTX/5wudhMXIsE1m/oRF0Nkm4HsV/qvPIWfLhUceoh0lnSEF etZ3jI3v9hZ2WozUAsgIopwOAPryn+EIO1Bp9RQePOozBFYZ4aypdZglYXtrhK/LA6LfnMs IpXLg5kF/6n1fQlG1SyoVU3FxrCPHVKWg4/+sg1zCcZXWDonppEb2pTCLt7eV+yorDtn7WF fFaKyv6f5YmznWS4qqpt6suYymgL+Em1NpwwXHGeQncMwNq5nAmkL7cvS21uRN5t4qfzfwo 4N5uTn3E/wgGxzcgVdnFqR+R2jj2Ls7yn/suk/AtWRFK4vA09k3UHvFkVuzNuo6PsPUfJEH aU/DG5kMkEJSvY/2o6OrA8LS2QDb8S00uO4Nw6vEAV5HHA4s8wbE/EF9Uqt9GUp72KFW881 mn6b4VH4Xn2axhcM1yhMRFofNZSu2dyn8m7A6MSwx4GV2O+0+wZy/qZvtK7dnTUYEHy4Ktj ooMMJlYDlq3fhmww1VPRVivc2/IxleJ7DbaahE/YTGRJwFAHNx6GJPL1L4P6pjRIfEP7uNX VT94hIE+HMg4gG6zeu7XU4rUOQ13tBMOFn85H3MsilkJ2WZEWPwKDc+ApqkXPA1gAlvryjK NNmjSGIA== X-QQ-XMRINFO: NyFYKkN4Ny6FuXrnB5Ye7Aabb3ujjtK+gg== X-QQ-RECHKSPAM: 0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260602_203641_110875_FFC11DDF X-CRM114-Status: GOOD ( 12.58 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Chaoyi Chen Different chips have varying support for the maximum bit rate per lane. Add calculation for the maximum per lane bit rate for various chip platforms. Signed-off-by: Chaoyi Chen --- Changes in v2: - Fix the unit conversion for max_mbps. - Split the lane rate calculation into a separate patch. --- drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c index 3547d91b25d3..1060abec9f29 100644 --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c @@ -268,6 +268,7 @@ struct rockchip_dw_dsi_chip_data { unsigned int flags; unsigned int max_data_lanes; + unsigned long max_bit_rate_per_lane; }; struct dw_mipi_dsi_rockchip { @@ -565,7 +566,7 @@ dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct drm_display_mode *mode, int bpp; unsigned long mpclk, tmp; unsigned int target_mbps = 1000; - unsigned int max_mbps = dppa_map[ARRAY_SIZE(dppa_map) - 1].max_mbps; + unsigned int max_mbps; unsigned long best_freq = 0; unsigned long fvco_min, fvco_max, fin, fout; unsigned int min_prediv, max_prediv; @@ -573,6 +574,7 @@ dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct drm_display_mode *mode, unsigned long _fbdiv, best_fbdiv; unsigned long min_delta = ULONG_MAX; + max_mbps = dsi->cdata->max_bit_rate_per_lane / USEC_PER_SEC; dsi->format = format; bpp = mipi_dsi_pixel_format_to_bpp(dsi->format); if (bpp < 0) { @@ -1503,6 +1505,7 @@ static const struct rockchip_dw_dsi_chip_data px30_chip_data[] = { PX30_DSI_FORCETXSTOPMODE), 0), .max_data_lanes = 4, + .max_bit_rate_per_lane = 1000000000UL, }, { /* sentinel */ } }; @@ -1515,6 +1518,7 @@ static const struct rockchip_dw_dsi_chip_data rk3128_chip_data[] = { RK3128_DSI_FORCERXMODE | RK3128_DSI_FORCETXSTOPMODE), 0), .max_data_lanes = 4, + .max_bit_rate_per_lane = 1000000000UL, }, { /* sentinel */ } }; @@ -1527,6 +1531,7 @@ static const struct rockchip_dw_dsi_chip_data rk3288_chip_data[] = { .lcdsel_lit = FIELD_PREP_WM16_CONST(RK3288_DSI0_LCDC_SEL, 1), .max_data_lanes = 4, + .max_bit_rate_per_lane = 1500000000UL, }, { .reg = 0xff964000, @@ -1535,6 +1540,7 @@ static const struct rockchip_dw_dsi_chip_data rk3288_chip_data[] = { .lcdsel_lit = FIELD_PREP_WM16_CONST(RK3288_DSI1_LCDC_SEL, 1), .max_data_lanes = 4, + .max_bit_rate_per_lane = 1500000000UL, }, { /* sentinel */ } }; @@ -1547,6 +1553,7 @@ static const struct rockchip_dw_dsi_chip_data rk3368_chip_data[] = { RK3368_DSI_FORCETXSTOPMODE | RK3368_DSI_FORCERXMODE), 0), .max_data_lanes = 4, + .max_bit_rate_per_lane = 1500000000UL, }, { /* sentinel */ } }; @@ -1634,6 +1641,7 @@ static const struct rockchip_dw_dsi_chip_data rk3399_chip_data[] = { .flags = DW_MIPI_NEEDS_PHY_CFG_CLK | DW_MIPI_NEEDS_GRF_CLK, .max_data_lanes = 4, + .max_bit_rate_per_lane = 1500000000UL, }, { .reg = 0xff968000, @@ -1658,6 +1666,7 @@ static const struct rockchip_dw_dsi_chip_data rk3399_chip_data[] = { .flags = DW_MIPI_NEEDS_PHY_CFG_CLK | DW_MIPI_NEEDS_GRF_CLK, .max_data_lanes = 4, + .max_bit_rate_per_lane = 1500000000UL, .dphy_rx_init = rk3399_dphy_tx1rx1_init, .dphy_rx_power_on = rk3399_dphy_tx1rx1_power_on, @@ -1674,6 +1683,7 @@ static const struct rockchip_dw_dsi_chip_data rk3506_chip_data[] = { FIELD_PREP_WM16_CONST(RK3506_DSI_FORCERXMODE, 0) | FIELD_PREP_WM16_CONST(RK3506_DSI_FORCETXSTOPMODE, 0)), .max_data_lanes = 2, + .max_bit_rate_per_lane = 1500000000UL, }, { /* sentinel */ } }; @@ -1687,6 +1697,7 @@ static const struct rockchip_dw_dsi_chip_data rk3568_chip_data[] = { FIELD_PREP_WM16_CONST(RK3568_DSI0_TURNDISABLE, 0) | FIELD_PREP_WM16_CONST(RK3568_DSI0_FORCERXMODE, 0)), .max_data_lanes = 4, + .max_bit_rate_per_lane = 1200000000UL, }, { .reg = 0xfe070000, @@ -1696,6 +1707,7 @@ static const struct rockchip_dw_dsi_chip_data rk3568_chip_data[] = { FIELD_PREP_WM16_CONST(RK3568_DSI1_TURNDISABLE, 0) | FIELD_PREP_WM16_CONST(RK3568_DSI1_FORCERXMODE, 0)), .max_data_lanes = 4, + .max_bit_rate_per_lane = 1200000000UL, }, { /* sentinel */ } }; @@ -1708,6 +1720,7 @@ static const struct rockchip_dw_dsi_chip_data rv1126_chip_data[] = { FIELD_PREP_WM16_CONST(RV1126_DSI_FORCERXMODE, 0) | FIELD_PREP_WM16_CONST(RV1126_DSI_FORCETXSTOPMODE, 0)), .max_data_lanes = 4, + .max_bit_rate_per_lane = 1000000000UL, }, { /* sentinel */ } }; -- 2.53.0