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Thu, 04 Jun 2026 06:53:00 -0700 (PDT) Received: from compiler-rock3b.tailb81abf.ts.net ([2a01:e0a:104a:4d80:be24:11ff:fe12:2776]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4601f0a43e9sm16661068f8f.0.2026.06.04.06.52.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Jun 2026 06:52:59 -0700 (PDT) From: Midgy BALON To: tomeu@tomeuvizoso.net, ogabbay@kernel.org, heiko@sntech.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, joro@8bytes.org, will@kernel.org Cc: robin.murphy@arm.com, dri-devel@lists.freedesktop.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [RFC PATCH v3 3/9] accel: rocket: Add RK3568 SoC support Date: Thu, 4 Jun 2026 13:52:49 +0000 Message-Id: <20260604135255.62682-4-midgy971@gmail.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20260604135255.62682-1-midgy971@gmail.com> References: <20260604135255.62682-1-midgy971@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260604_145301_828357_F9410A71 X-CRM114-Status: GOOD ( 17.98 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The RK3568 has a single core of the same NVDLA-derived NPU IP as the RK3588, with a 32-bit AXI master. Unlike the RK3588 it must be powered on and de-idled through the PMU, and its PVTPLL clock started via SCMI, before the NPU is reachable. Add rk3568_soc_data with an noc_init callback performing this bring-up. Signed-off-by: Midgy BALON --- drivers/accel/rocket/rocket_core.c | 9 +++++ drivers/accel/rocket/rocket_core.h | 3 ++ drivers/accel/rocket/rocket_drv.c | 53 ++++++++++++++++++++++++++++++ 3 files changed, 65 insertions(+) diff --git a/drivers/accel/rocket/rocket_core.c b/drivers/accel/rocket/rocket_core.c index 09c445af7de73..a8de876365873 100644 --- a/drivers/accel/rocket/rocket_core.c +++ b/drivers/accel/rocket/rocket_core.c @@ -88,6 +88,15 @@ int rocket_core_init(struct rocket_core *core) return err; } + if (core->soc_data->noc_init) { + err = core->soc_data->noc_init(core); + if (err) { + pm_runtime_put_sync(dev); + rocket_job_fini(core); + return err; + } + } + version = rocket_pc_readl(core, VERSION); version += rocket_pc_readl(core, VERSION_NUM) & 0xffff; diff --git a/drivers/accel/rocket/rocket_core.h b/drivers/accel/rocket/rocket_core.h index d6421251670dc..66d138a8ed773 100644 --- a/drivers/accel/rocket/rocket_core.h +++ b/drivers/accel/rocket/rocket_core.h @@ -18,10 +18,13 @@ struct rocket_core; * struct rocket_soc_data - per-SoC configuration data * @num_cores: Number of NPU cores in this SoC. * @dma_bits: Physical address width reachable by the NPU's AXI master. + * @noc_init: Optional callback to power on and de-idle the NPU NOC bus. + * Required on RK3568, where this is done through the PMU. */ struct rocket_soc_data { unsigned int num_cores; unsigned int dma_bits; + int (*noc_init)(struct rocket_core *core); }; #define rocket_pc_readl(core, reg) \ diff --git a/drivers/accel/rocket/rocket_drv.c b/drivers/accel/rocket/rocket_drv.c index c18840e5aff76..5a72d0b5f4dff 100644 --- a/drivers/accel/rocket/rocket_drv.c +++ b/drivers/accel/rocket/rocket_drv.c @@ -9,9 +9,11 @@ #include #include #include +#include #include #include #include +#include #include "rocket_device.h" #include "rocket_drv.h" @@ -217,12 +219,63 @@ static void rocket_remove(struct platform_device *pdev) } } +/* + * On RK3568 the NPU NOC bus is gated and idle out of reset and must be + * powered on and de-idled through the PMU before the NPU is reachable. PMU + * registers use a write-mask protocol: the upper 16 bits enable writes to the + * matching lower 16 bits. + * + * The NPU's high-speed clock is a PVTPLL managed by TF-A via SCMI and must be + * running before the NOC acknowledges the de-idle request. Force a real SCMI + * rate change (an intermediate rate defeats the clock framework's + * unchanged-rate shortcut) now that the power domain is on and clocks enabled. + */ +#define ROCKET_RK3568_SCMI_CLK 2 + +static int rk3568_noc_init(struct rocket_core *core) +{ + struct regmap *pmu; + unsigned int val; + int ret; + + clk_set_rate(core->clks[ROCKET_RK3568_SCMI_CLK].clk, 600000000UL); + clk_set_rate(core->clks[ROCKET_RK3568_SCMI_CLK].clk, 1000000000UL); + + pmu = syscon_regmap_lookup_by_phandle(core->dev->of_node, "rockchip,pmu"); + if (IS_ERR(pmu)) + return dev_err_probe(core->dev, PTR_ERR(pmu), + "failed to get PMU regmap\n"); + + /* Power on the NPU power domain (PWR_GATE_SFTCON bit 1 = 0). */ + regmap_write(pmu, 0xa0, BIT(1 + 16)); + + /* Disable NPU NOC auto-idle (NOC_AUTO_CON0 bit 2). */ + regmap_write(pmu, 0x70, BIT(2 + 16)); + + /* Request NPU bus de-idle (BUS_IDLE_SFTCON0 bit 2 = 0). */ + regmap_write(pmu, 0x50, BIT(2 + 16)); + + /* Wait for the bus to report active (BUS_IDLE_ST bit 2 = 0). */ + ret = regmap_read_poll_timeout(pmu, 0x68, val, !(val & BIT(2)), 10, 1000); + if (ret) + dev_err(core->dev, "timed out waiting for NPU bus de-idle\n"); + + return ret; +} + +static const struct rocket_soc_data rk3568_soc_data = { + .num_cores = 1, + .dma_bits = 32, + .noc_init = rk3568_noc_init, +}; + static const struct rocket_soc_data rk3588_soc_data = { .num_cores = 3, .dma_bits = 40, }; static const struct of_device_id dt_match[] = { + { .compatible = "rockchip,rk3568-rknn-core", .data = &rk3568_soc_data }, { .compatible = "rockchip,rk3588-rknn-core", .data = &rk3588_soc_data }, {} }; -- 2.39.5