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[47.54.130.67]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-51775e2e16dsm80797461cf.31.2026.06.05.07.10.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Jun 2026 07:10:54 -0700 (PDT) Received: from jgg by wakko with local (Exim 4.97) (envelope-from ) id 1wVVG9-0000000BEgc-3cQ9; Fri, 05 Jun 2026 11:10:53 -0300 Date: Fri, 5 Jun 2026 11:10:53 -0300 From: Jason Gunthorpe To: Ashish Mhetre Cc: Will Deacon , robin.murphy@arm.com, joro@8bytes.org, nicolinc@nvidia.com, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org Subject: Re: [PATCH v3 2/3] iommu/arm-smmu-v3: Detect Tegra264 erratum Message-ID: <20260605141053.GF2487554@ziepe.ca> References: <20260601104845.995005-1-amhetre@nvidia.com> <20260601104845.995005-3-amhetre@nvidia.com> <09a501ff-d1e8-4035-95c1-a6df9f0cb9d0@nvidia.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <09a501ff-d1e8-4035-95c1-a6df9f0cb9d0@nvidia.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260605_071057_908850_A064AB27 X-CRM114-Status: GOOD ( 14.59 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, Jun 05, 2026 at 07:35:35PM +0530, Ashish Mhetre wrote: > > > +{ > > > + if (!(smmu->options & ARM_SMMU_OPT_TLBI_TWICE)) > > > + return false; > > Maybe we should make this a static key? > > Okay. Shall I add just static key and remove option bit, or > have static key alongside existing option bit such that > static_branch_unlikely will precede the option bit check? You'd have the static key and the options. Keep it simple, enable the static key once if any driver probes to set TWICE. Check the key before options to get the best code gen But IDK if it is really worth it, there are already lots of branches on the performance tlbi flow, and we didn't do this for other tlbi affecting errata.. IDK if we really care about branches we should also be doing things like disabling the range/non-range paths and ATC based on what is actually in use.. Jason