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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?7abrtNJ+AYNxVtIN4NiE/9GKLCm47dY/0kLoTAUzrwc+gVecxc18NjT2rp8g?= =?us-ascii?Q?sf2mKp7VvGpAfnsRTajvj3sd8IUEOaSXrgvvr78hj7ZqsarwGZfdX5A+i1xe?= =?us-ascii?Q?1/T9FsfC1r1R4GDST53eK02/yYkCoJHZYervfUYlScg9i78r114zfgLZ8c3r?= =?us-ascii?Q?uvudjxjhDlpWiYGNngCmscahC/lDYl+8y5kzduEeeJtw7QojCokA/91kjmQX?= =?us-ascii?Q?eDSowC9R7k9Qqj+OiYij32dI+GEDofyvistoROx6H9bFcbHyL6cln2BuF4Xb?= =?us-ascii?Q?P2hzeQJ7Q5bhxj6INsaqa5slTcIwxL/+sQD3Sfqpao3pZzx+mGsOEbfTYKXH?= =?us-ascii?Q?kAV3UXKpDR4izP8SCHPWb+rO2LxENAHxVR8h1WJH8IFVIUyZfTsxWAavZuBf?= =?us-ascii?Q?+XuS0g1KzsCFynQQn9NX83RR5NF++/Glxxgho4uYarhRO1i49UwlN4BhzjAu?= =?us-ascii?Q?g+6upu/vyxvMvDTA5/J+d6HaRRWMOvnNknTA4X2WeW7ZJo/VjOglzd8SBxLs?= =?us-ascii?Q?kCXHDvvkN5hFtVT8CoHP4cCPjmQ9YSFfp5LCn1JbfyLT0H3YZ5z5drfCxNV+?= =?us-ascii?Q?LnMc5T80fGikmP40DYsqDTgJBy7ENFIfVc0ijCYP9dCWq6vJVNx/n1EnQohK?= =?us-ascii?Q?aKNP71RdgEecS9UqShlkxqJliH0wOQ7DCjThsF/L/wxzYgHe2D6GpZjnVWHu?= =?us-ascii?Q?BvNjcFoaXc+y8yqABtZbkhjaWfgq9pHc4ynI5BIDy+ck1oGMs4ndJk3EM2dQ?= =?us-ascii?Q?Hg/LdQYMu8JFk97Jw/WhoGmTqD9zJRAEmUK+Bq4SvkFDupqVsSrSGBEosB1I?= =?us-ascii?Q?q4UGs9qn5+Ub4YjuyplWOFOZ85gvsvZkh0sp4qHGTFZNqP6+jjgDVEoxO914?= =?us-ascii?Q?AAVdTSBEDBpdAD0SHid2gyAlSZN2b8L1Gmh0Sh+Yz7QpdSLUMw6vm1jySTyT?= =?us-ascii?Q?qIGwnypj5tAqTU97GlvSZtJgD+7oszQCCwZwNggZbcheqBG5wKgGuQqFYOHo?= =?us-ascii?Q?Kmc9HSpMj7pfOtuEUUHI3TvHjTJ2dYuHutqb0ZGInu2ERwJxZ+ZlHT7xvOhT?= =?us-ascii?Q?oHKY7ffjNNAPnZgCbxmV/uKQQ0Rzqnt5DsS3KkNt09xi5gl3cCNyqzkC5tzF?= =?us-ascii?Q?B8DUYYGhX6HW/x92Ek77qS0Ve1gUDMPTk2ArYbjSB36GsVaoatrAacldf6pa?= =?us-ascii?Q?eKu7vZ42lcezXsJuBmN3YA/EbFu++zsrp9IslQizcj1Fl5bjPWlW9HIFHVGz?= =?us-ascii?Q?K3ABppkETJZ1EvWRYumuVX2MWVZznmMBcFI15O9WpBGMNWSFmOL7YdjaMj2+?= =?us-ascii?Q?oqXkOOlSJM8CByWuG862OVvuSHZ/PExXTiIBxSEJBA4F1hsFZgc8+SGaxsol?= =?us-ascii?Q?4tSJN6SmzCoPcwpwy2NGIUjhsa9r36t+MHeD1tzPsko+j0Eg8lf3xQcAvWef?= =?us-ascii?Q?SR7PiFPZvDbZPveJpy26cTeseEiIrDMk6CL7m1ylBSr08QUk6yYpikBQ/c1i?= =?us-ascii?Q?fmhjd/oTzVVZ92VlwT6/RbN/h8TVJshIe49KAht7jt8tsK777a6B2TwrZ0Z3?= =?us-ascii?Q?HefmZYY1B06v6/Acx4kIphpsSwe1RhAfjBBzkx+odi5V2Vuk0WuXs9pg3khs?= =?us-ascii?Q?kV1XIGEr7K4IaGhVS+shzjBcSHxKz5ATHRhpJqnwsie+a+5qzlVAZ3a7koxM?= =?us-ascii?Q?ZnAbapPlYKEn5/qwXw2WXKrdcAGKxXwXNhBx5Sbce0GaSSTi?= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 917b9185-e4d5-476a-4853-08dec33aa691 X-MS-Exchange-CrossTenant-AuthSource: LV8PR12MB9620.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Jun 2026 19:43:00.6433 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: KCqGiUkVCZZWGANpEaQvmKxPmlT4Pqk8danO3Q/uj6zLPcNOm7S1/TgYp7Nvvilv X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB6190 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260605_124310_401462_78A52B79 X-CRM114-Status: GOOD ( 35.53 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, Jun 01, 2026 at 10:44:36PM -0700, Nicolin Chen wrote: > On Mon, Jun 01, 2026 at 09:15:47PM -0300, Jason Gunthorpe wrote: > > On Mon, Jun 01, 2026 at 01:41:26PM -0700, Nicolin Chen wrote: > > > On Mon, Jun 01, 2026 at 09:32:31AM -0300, Jason Gunthorpe wrote: > > > > On Fri, May 29, 2026 at 06:27:40PM -0700, Nicolin Chen wrote: > > > > > On Tue, May 19, 2026 at 09:06:58AM -0300, Jason Gunthorpe wrote: > > > > > > On Mon, May 18, 2026 at 08:39:01PM -0700, Nicolin Chen wrote: > > > > > So I've tried INV_TYPE_ATS_BROKEN: during per-domain invalidation, > > > > > each batch is built from domain->invs so it can carry the "invs"; > > > > > if the batch times out, we can immediately mutate its ATS entries. > > > > > > > > > > But I realized a limitation. E.g., if a device attaches to two SVA > > > > > domains on two SSIDs. An invalidation timing out on one of the SVA > > > > > domains could mark INV_TYPE_ATS_BROKEN in its own invs, but not in > > > > > the other SVA domain's invs? > > > > > > > > You'd have to mark all the S1's sharing the STE. > > > > > > That would be a bit convoluted as we would have to go through all > > > other domains' invs arrays. > > > > Ok, that is certainly an annoying problem. > > > > I don't have a better idea than storing the master unfortunately > > > > But I think the locking for that is going to be tricky, I'm not sure it does > > actually fully work.. > > Yes, there can be a race that sets STE.EATS back while per-master > flag is set, which would skip the ATC_INV in commit(), so no more > ATC_INV timeout that resets STE.EATS=0. To close it, we can force > STE.EATS=0 at the end of commit() when state->ats_enabled and the > per-master flag are both set, which is only possible in a race. I don't see any of these options as appealing. We have to maintain a few key invariants, and I think it cannot be done without a way to find all the domains that are using the STE. One way or another you have to be using the invs list rw locks to synchronize the EATS state changes. It is okayish to be sloppy when turning EATS off, but when turning it back on we do need to cycle through every invs list and toggle its lock to ensure that the invalidations are synchronized before EATS=enable happens. Given you must have a way to go from STE -> master -> all invs lists I'm not sure either option really makes such a large difference. If so then adjusting the invs to disable the ATS is pretty simple, run over the xarray and set them all off. Yes you could find the master through a SID lookup with some locking adjustment. > > (1) Per-invs marker: INV_TYPE_ATS_BROKEN + master_domains > disable_ats() in the timeout path walks master->master_domains > and flips matching ATS invs entries to the BROKEN type. > > + invs walker is free (one case label in the existing type switch). > + No lock or pointer deref in the invs walker. > + No master pointer stored in invs; no lifetime concern. > > - disable_ats() walks every (master, domain) and marks each invs > set; the list needs locking usable from atomic. This doesn't seem so bad > (2) Per-master flag + streams_lock > invs walker resolves SID -> master via streams_lock and reads > master->ats_broken. > > + Single source of truth on the master. > + disable_ats() is one WRITE_ONCE. > + atc_inv_master early-skips via one READ_ONCE. > + attach gates ats_enabled on the flag; a concurrent quarantine > race can be closed by a short post-attach re-check in commit() > + No master pointer in invs; no lifetime concern. > > - invs walker pays streams_lock + rb_find(SID) per ATS entry on > every invalidation. Measurable on ATS-heavy workloads. Doesn't consider how to enable > (3) Per-master flag + inv->master pointer (v4) > invs entry carries a master pointer; the invs walker reads > cur->master->ats_broken directly. > > + invs walker is one READ_ONCE through a cached pointer. > + disable_ats is one WRITE_ONCE. > + atc_inv_master early-skip via one READ_ONCE. > + attach gate + post-attach re-check, same as (2). > > - invs holds a master ptr, so release_device must synchronize_rcu() > before freeing the master to drain walkers under rcu_read_lock(). > We dropped this from v4 for that reason. synchronize_rcu is not right because you have to have gone through the rwlock so there can be no readers. Jason