From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E9E40CD8CAA for ; Tue, 9 Jun 2026 10:12:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=I2slIYfscyWeS05zMEpc2jKIRsHaYoq6eM2sVqreX8o=; b=DJ8N+xbXtteMgdF7F1ysiVW5ik sPb3QHxHCNFoY6wKyG4M3a6pS+itMqiuXz0UBwYWP3z2XLppOQXWDN/aPH8IsyeYz4zROH2bdTpMn n7/y1j34cB+B+JkzcvQSYTtXB+3kKmTJbrBrY+nfpCUp0+bfbTrUzarMvOhX9q8WDxG0krIR3QJ8y PgivaVHg+7XEkE1I/twhVM4ssY7dR0wsRh9OQvgDD7nVKheR7QJMzyxL3qVmKr4TLqEfEpX/jvwnH XIq/W7PyfUfAcEZ2OHqJnfvuMrtQfv767s2ZPX1Du0F0Cm3snjZ9qvmws5+UQS4j3yUEGzOw47tVn V9zvxd5w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.99.1 #2 (Red Hat Linux)) id 1wWtRt-00000005JQG-3TCu; Tue, 09 Jun 2026 10:12:45 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.99.1 #2 (Red Hat Linux)) id 1wWtRo-00000005JMd-2O2c for linux-arm-kernel@lists.infradead.org; Tue, 09 Jun 2026 10:12:42 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 22DE035B7; Tue, 9 Jun 2026 03:12:35 -0700 (PDT) Received: from lakrids.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 2BCB03FDBD; Tue, 9 Jun 2026 03:12:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1780999959; bh=yL+eM8FbxKNnDXbkYPDi9Towm3nwyTuM7d/MC++N8tY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=knBTNoATg156KSM99P6pf2TEC6UrjkqxOyMqxVAplRWIqLpkerd3Nip1MWUs6Xxef A+0bQdrPC188YyFu44q3hrGTGdyGbmQWT81zekzi614CHAJopM/LD7Gav8JaQEaaUW 1i3wbvX2aRis6BKRlnpa/Y9ThpIbQYvEpa+b3GsE= From: Mark Rutland To: linux-arm-kernel@lists.infradead.org Cc: catalin.marinas@arm.com, mark.rutland@arm.com, will@kernel.org Subject: [PATCH 2/3] arm64: cputype: Add C1-Premium definitions Date: Tue, 9 Jun 2026 11:12:02 +0100 Message-Id: <20260609101203.1512409-3-mark.rutland@arm.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20260609101203.1512409-1-mark.rutland@arm.com> References: <20260609101203.1512409-1-mark.rutland@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260609_031240_657416_CDDB1E5B X-CRM114-Status: UNSURE ( 9.37 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add cputype definitions for C1-Premium. These will be used for errata detection in subsequent patches. These values can be found in the C1-Premium TRM: https://developer.arm.com/documentation/109416/0100/ ... in section A.5.1 ("MIDR_EL1, Main ID Register"). Signed-off-by: Mark Rutland Cc: Catalin Marinas Cc: Will Deacon --- arch/arm64/include/asm/cputype.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h index 3e223a7781866..1b9f0cda1336d 100644 --- a/arch/arm64/include/asm/cputype.h +++ b/arch/arm64/include/asm/cputype.h @@ -100,6 +100,7 @@ #define ARM_CPU_PART_C1_ULTRA 0xD8C #define ARM_CPU_PART_NEOVERSE_N3 0xD8E #define ARM_CPU_PART_C1_PRO 0xD8B +#define ARM_CPU_PART_C1_PREMIUM 0xD90 #define APM_CPU_PART_XGENE 0x000 #define APM_CPU_VAR_POTENZA 0x00 @@ -193,6 +194,7 @@ #define MIDR_C1_ULTRA MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_C1_ULTRA) #define MIDR_NEOVERSE_N3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N3) #define MIDR_C1_PRO MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_C1_PRO) +#define MIDR_C1_PREMIUM MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_C1_PREMIUM) #define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX) #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX) #define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX) -- 2.30.2