From: Chun-Tse Shao <ctshao@google.com>
To: peterz@infradead.org, mingo@redhat.com, acme@kernel.org,
namhyung@kernel.org
Cc: alexander.shishkin@linux.intel.com, jolsa@kernel.org,
irogers@google.com, adrian.hunter@intel.com,
james.clark@linaro.org, afaerber@suse.de, mani@kernel.org,
dapeng1.mi@linux.intel.com, linux-perf-users@vger.kernel.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-actions@lists.infradead.org,
Chun-Tse Shao <ctshao@google.com>
Subject: [PATCH v1 2/6] perf vendor events intel: Update emeraldrapids events from 1.23 to 1.24
Date: Tue, 9 Jun 2026 14:50:41 -0700 [thread overview]
Message-ID: <20260609215046.2391903-3-ctshao@google.com> (raw)
In-Reply-To: <20260609215046.2391903-1-ctshao@google.com>
The updated events were published in:
https://github.com/intel/perfmon/commit/3f1d40d1953193e75c6b5a559638cf1f67bacaed
Signed-off-by: Chun-Tse Shao <ctshao@google.com>
---
tools/perf/pmu-events/arch/x86/emeraldrapids/cache.json | 9 +++++++++
tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +-
2 files changed, 10 insertions(+), 1 deletion(-)
diff --git a/tools/perf/pmu-events/arch/x86/emeraldrapids/cache.json b/tools/perf/pmu-events/arch/x86/emeraldrapids/cache.json
index ff6071d7728e..a44e1f027c1d 100644
--- a/tools/perf/pmu-events/arch/x86/emeraldrapids/cache.json
+++ b/tools/perf/pmu-events/arch/x86/emeraldrapids/cache.json
@@ -368,6 +368,15 @@
"SampleAfterValue": "200003",
"UMask": "0x40"
},
+ {
+ "BriefDescription": "Cycles when L1D is locked",
+ "Counter": "0,1,2,3",
+ "EventCode": "0x42",
+ "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION",
+ "PublicDescription": "This event counts the number of cycles when the L1D is locked. It is a superset of the 0x1 mask (BUS_LOCK_CLOCKS.BUS_LOCK_DURATION).",
+ "SampleAfterValue": "2000003",
+ "UMask": "0x2"
+ },
{
"BriefDescription": "Core-originated cacheable requests that missed L3 (Except hardware prefetches to the L3)",
"Counter": "0,1,2,3,4,5,6,7",
diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-events/arch/x86/mapfile.csv
index 613881d04a9a..0f39073805ba 100644
--- a/tools/perf/pmu-events/arch/x86/mapfile.csv
+++ b/tools/perf/pmu-events/arch/x86/mapfile.csv
@@ -9,7 +9,7 @@ GenuineIntel-6-4F,v23,broadwellx,core
GenuineIntel-6-55-[56789ABCDEF],v1.25,cascadelakex,core
GenuineIntel-6-DD,v1.02,clearwaterforest,core
GenuineIntel-6-9[6C],v1.05,elkhartlake,core
-GenuineIntel-6-CF,v1.23,emeraldrapids,core
+GenuineIntel-6-CF,v1.24,emeraldrapids,core
GenuineIntel-6-5[CF],v13,goldmont,core
GenuineIntel-6-7A,v1.01,goldmontplus,core
GenuineIntel-6-B6,v1.12,grandridge,core
--
2.54.0.1099.g489fc7bff1-goog
next prev parent reply other threads:[~2026-06-09 21:51 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-06-09 21:50 [PATCH v1 0/6] perf vendor events intel: update Chun-Tse Shao
2026-06-09 21:50 ` [PATCH v1 1/6] perf vendor events intel: Update arrowlake events from 1.17 to 1.19 Chun-Tse Shao
2026-06-09 21:50 ` Chun-Tse Shao [this message]
2026-06-09 21:50 ` [PATCH v1 3/6] perf vendor events intel: Update graniterapids events from 1.18 " Chun-Tse Shao
2026-06-09 21:50 ` [PATCH v1 4/6] perf vendor events intel: Update lunarlake events from 1.22 to 1.25 Chun-Tse Shao
2026-06-09 21:50 ` [PATCH v1 5/6] perf vendor events intel: Update pantherlake events from 1.05 to 1.06 Chun-Tse Shao
2026-06-09 21:50 ` [PATCH v1 6/6] perf vendor events intel: Update tigerlake events from 1.18 to 1.19 Chun-Tse Shao
2026-06-15 1:32 ` [PATCH v1 0/6] perf vendor events intel: update Mi, Dapeng
2026-06-15 15:37 ` Ian Rogers
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