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Wed, 10 Jun 2026 14:17:15 +0800 (CST) From: joakim.zhang@cixtech.com To: mturquette@baylibre.com, sboyd@kernel.org, bmasney@redhat.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, gary.yang@cixtech.com Cc: cix-kernel-upstream@cixtech.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Joakim Zhang Subject: [PATCH v3 1/5] dt-bindings: soc: cix,sky1-system-control: add audss system control Date: Wed, 10 Jun 2026 14:17:08 +0800 Message-ID: <20260610061712.3203984-2-joakim.zhang@cixtech.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20260610061712.3203984-1-joakim.zhang@cixtech.com> References: <20260610061712.3203984-1-joakim.zhang@cixtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SG2PEPF000B66CA:EE_|KL1PR06MB6297:EE_ Content-Type: text/plain X-MS-Office365-Filtering-Correlation-Id: 60330e5a-907a-4e02-afc2-08dec6b7eb93 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|23010399003|7416014|376014|1800799024|82310400026|56012099006|6133799003|22082099003|18002099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: VYn1FqnNeCc4KlKNsSeAL/lWY2ZA9tCuG73NPkQnW6EVmAUoNoqu/La5g6yuyqd6zGUwrUBVsXNuzkbr3uBDvqnK4ekPJrOYu0PpefctgTfwavmrqOhwpYjK+FdnbmkDXhuD9UE2qc2ueSWYWhnAMkN2TVEa36bhZSX0s95pes7GHTbnqKVxhMUhpsSNQsnSBKe5xyoA5BptbiXZyAi1XFRqy6+be2jGMDLolaiSbybQaPKwJzkqtyMsNT0et23xMkhTqg14WLTFEo995RPWKfRughBgx9EmTYnpVwLbqMzayc/LJLbOe+9mcv5DRnqads97pmf77Q8zij7b5VxM4cbEiTjNjIzF3tK8VYfxQ/qw8SBPj6SZK+uSlxERsmQaUEalbi2g7Du39AbV9dqapkSNmiIDtznMI0EaDxlCuDwtsuNZLrlTXDsglVn3Ns71 X-OriginatorOrg: cixtech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Jun 2026 06:17:16.4966 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 60330e5a-907a-4e02-afc2-08dec6b7eb93 X-MS-Exchange-CrossTenant-Id: 0409f77a-e53d-4d23-943e-ccade7cb4811 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0409f77a-e53d-4d23-943e-ccade7cb4811;Ip=[222.71.101.198];Helo=[smtprelay.cixcomputing.com] X-MS-Exchange-CrossTenant-AuthSource: SG2PEPF000B66CA.apcprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: KL1PR06MB6297 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260609_231729_614535_3E6A3881 X-CRM114-Status: GOOD ( 13.73 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Joakim Zhang The Cix Sky1 Audio Subsystem (AUDSS) groups audio-related clock, reset and control registers in a dedicated CRU block. Software reset lines are exposed on the syscon parent via #reset-cells, following the same model as the existing Sky1 FCH and S5 system control bindings. Add the cix,sky1-audss-system-control compatible to cix,sky1-system-control.yaml for the MFD/syscon parent node, and define AUDSS software reset indices in include/dt-bindings/reset/cix,sky1-audss-system-control.h for I2S, HDA, DMAC, mailbox, watchdog and timer blocks. Signed-off-by: Joakim Zhang --- .../soc/cix/cix,sky1-system-control.yaml | 47 +++++++++++++++++-- .../reset/cix,sky1-audss-system-control.h | 25 ++++++++++ 2 files changed, 67 insertions(+), 5 deletions(-) create mode 100644 include/dt-bindings/reset/cix,sky1-audss-system-control.h diff --git a/Documentation/devicetree/bindings/soc/cix/cix,sky1-system-control.yaml b/Documentation/devicetree/bindings/soc/cix/cix,sky1-system-control.yaml index a01a515222c6..6c887b04cf25 100644 --- a/Documentation/devicetree/bindings/soc/cix/cix,sky1-system-control.yaml +++ b/Documentation/devicetree/bindings/soc/cix/cix,sky1-system-control.yaml @@ -15,11 +15,16 @@ description: properties: compatible: - items: - - enum: - - cix,sky1-system-control - - cix,sky1-s5-system-control - - const: syscon + oneOf: + - items: + - enum: + - cix,sky1-system-control + - cix,sky1-s5-system-control + - const: syscon + - items: + - const: cix,sky1-audss-system-control + - const: simple-mfd + - const: syscon reg: maxItems: 1 @@ -27,6 +32,28 @@ properties: '#reset-cells': const: 1 + clock-controller: + type: object + properties: + compatible: + const: cix,sky1-audss-clock + required: + - compatible + additionalProperties: true + +allOf: + - if: + properties: + compatible: + contains: + const: cix,sky1-audss-system-control + then: + required: + - clock-controller + else: + properties: + clock-controller: false + required: - compatible - reg @@ -40,3 +67,13 @@ examples: reg = <0x4160000 0x100>; #reset-cells = <1>; }; + - | + audss_syscon: system-controller@7110000 { + compatible = "cix,sky1-audss-system-control", "simple-mfd", "syscon"; + reg = <0x7110000 0x10000>; + #reset-cells = <1>; + + clock-controller { + compatible = "cix,sky1-audss-clock"; + }; + }; diff --git a/include/dt-bindings/reset/cix,sky1-audss-system-control.h b/include/dt-bindings/reset/cix,sky1-audss-system-control.h new file mode 100644 index 000000000000..aabdce60b094 --- /dev/null +++ b/include/dt-bindings/reset/cix,sky1-audss-system-control.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ +/* + * Copyright 2026 Cix Technology Group Co., Ltd. + */ +#ifndef DT_BINDING_RESET_CIX_SKY1_AUDSS_SYSTEM_CONTROL_H +#define DT_BINDING_RESET_CIX_SKY1_AUDSS_SYSTEM_CONTROL_H + +#define AUDSS_I2S0_SW_RST 0 +#define AUDSS_I2S1_SW_RST 1 +#define AUDSS_I2S2_SW_RST 2 +#define AUDSS_I2S3_SW_RST 3 +#define AUDSS_I2S4_SW_RST 4 +#define AUDSS_I2S5_SW_RST 5 +#define AUDSS_I2S6_SW_RST 6 +#define AUDSS_I2S7_SW_RST 7 +#define AUDSS_I2S8_SW_RST 8 +#define AUDSS_I2S9_SW_RST 9 +#define AUDSS_WDT_SW_RST 10 +#define AUDSS_TIMER_SW_RST 11 +#define AUDSS_MB0_SW_RST 12 +#define AUDSS_MB1_SW_RST 13 +#define AUDSS_HDA_SW_RST 14 +#define AUDSS_DMAC_SW_RST 15 + +#endif -- 2.50.1