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Wysocki" , Danilo Krummrich , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno Cc: Alan Stern , Chen-Yu Tsai , linux-acpi@vger.kernel.org, driver-core@lists.linux.dev, linux-pm@vger.kernel.org, linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH v2 13/16] arm64: dts: mediatek: mt8192-asurada: Add M.2 E-key slot Date: Wed, 10 Jun 2026 16:40:47 +0800 Message-ID: <20260610084053.2059858-14-wenst@chromium.org> X-Mailer: git-send-email 2.54.0.1099.g489fc7bff1-goog In-Reply-To: <20260610084053.2059858-1-wenst@chromium.org> References: <20260610084053.2059858-1-wenst@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260610_014217_016212_D435499C X-CRM114-Status: GOOD ( 14.51 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The MT8192 Asurada design features an M.2 E-key slot for WiFi/BT combo cards. Only PCIe and USB are wired from the SoC to the slot, along with some auxiliary signals. Add the proper representation for it, replacing the PCIe wifi node and vpcie3v3-supply property under the PCIe controller. Also clean up the pcie controller node. Signed-off-by: Chen-Yu Tsai --- .../boot/dts/mediatek/mt8192-asurada.dtsi | 65 +++++++++++++++++-- 1 file changed, 58 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi index fb4d92750770..901240384a4a 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi @@ -318,6 +318,41 @@ usb_a_u3_ep: endpoint { }; }; }; + + wifi-bt-connector { + compatible = "pcie-m2-e-connector"; + pinctrl-names = "default"; + pinctrl-0 = <&m2_e_key_kill_pins>; + vpcie3v3-supply = <&pp3300_wlan>; + w-disable1-gpios = <&pio 61 GPIO_ACTIVE_LOW>; + w-disable2-gpios = <&pio 59 GPIO_ACTIVE_LOW>; + /* PCIe auxiliary signals wired to controller. */ + + ports { + #address-cells = <1>; + #size-cells = <0>; + + /* PCIe for WiFi */ + port@0 { + reg = <0>; + + wifi_ep: endpoint { + remote-endpoint = <&pcie_ep>; + }; + }; + + /* USB for Bluetooth */ + port@2 { + reg = <2>; + + bt_ep: endpoint { + remote-endpoint = <&usb2_hub_p4_ep>; + }; + }; + + /* SDIO, UART and I2S not implemented */ + }; + }; }; &afe { @@ -671,19 +706,19 @@ &pcie { pinctrl-0 = <&pcie_pins>; memory-region = <&wifi_restricted_dma_region>; - pcie0: pcie@0,0 { + pcie@0 { + compatible = "pciclass,0604"; + reg = <0 0 0 0 0>; device_type = "pci"; - reg = <0x0000 0 0 0 0>; num-lanes = <1>; - bus-range = <0x1 0x1>; - #address-cells = <3>; #size-cells = <2>; ranges; - wifi: wifi@0,0 { - reg = <0x10000 0 0 0 0x100000>, - <0x10000 0 0x100000 0 0x100000>; + port { + pcie_ep: endpoint { + remote-endpoint = <&wifi_ep>; + }; }; }; }; @@ -1206,6 +1241,14 @@ pins-bus { }; }; + m2_e_key_kill_pins: m2-e-key-kill-pins { + pins-kill { + pinmux = , + ; + output-high; + }; + }; + mmc0_default_pins: mmc0-default-pins { pins-cmd-dat { pinmux = , @@ -1773,6 +1816,14 @@ usb2_hub_p3_ep: endpoint { remote-endpoint = <&usb_a_u2_ep>; }; }; + + port@4 { + reg = <4>; + + usb2_hub_p4_ep: endpoint { + remote-endpoint = <&bt_ep>; + }; + }; }; }; }; -- 2.54.0.1099.g489fc7bff1-goog